Attention is currently required from: Furquan Shaikh, Sugnan Prabhu S, Subrata Banik, Tim Wawrzynczak, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51658 )
Change subject: soc/intel/alderlake: Add enum for HDA audio configuration ......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Done […]
Changes to ADLRVP & shadowmountain need to be included for this to compile, i.e.: ``` diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index d0cb5f16ac..0ab910a276 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -166,12 +166,9 @@ chip soc/intel/alderlake register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSndwEnable[0]" = "1" register "PchHdaAudioLinkSndwEnable[1]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0" + register "PchHdaIDispLinkTmode" = "HDA_TMODE_4T" + register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" + register "PchHdaIDispCodecEnable" = "1"
# Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 3094010584..cbd876a251 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -129,12 +129,10 @@ chip soc/intel/alderlake register "PchHdaAudioLinkDmicEnable[1]" = "1" register "PchHdaAudioLinkSndwEnable[0]" = "1" register "PchHdaAudioLinkSndwEnable[1]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0" + register "PchHdaIDispLinkTmode" = "HDA_TMODE_4T" + register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" + register "PchHdaIDispCodecEnable" = "1" +
# Intel Common SoC Config register "common_soc_config" = "{ diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index 4df80179b1..3a42ca10c8 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -117,12 +117,9 @@ chip soc/intel/alderlake register "PchHdaAudioLinkSspEnable[1]" = "0" register "PchHdaAudioLinkSndwEnable[0]" = "0" register "PchHdaAudioLinkSndwEnable[1]" = "0" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "3" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0" + register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T" + register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" + register "PchHdaIDispCodecEnable" = "1"
# DP port register "DdiPortAConfig" = "1" # eDP ```