Mimoja has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37579 )
Change subject: vendorcode/intel: Remove Ice Lake FSP Bindings ......................................................................
Patch Set 12:
(3 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/37579/9/src/drivers/intel/fsp2_0/in... File src/drivers/intel/fsp2_0/include/fsp/soc_binding.h:
https://review.coreboot.org/c/coreboot/+/37579/9/src/drivers/intel/fsp2_0/in... PS9, Line 20: /* : * This file is a implementation specific header. i.e. different : * FSP implementations for different chipsets. : */
Does somebody understand this comment??? […]
Done
https://review.coreboot.org/c/coreboot/+/37579/9/src/drivers/intel/fsp2_0/in... PS9, Line 24:
Please add a comment that the below block needs to be here to fix […]
Done
https://review.coreboot.org/c/coreboot/+/37579/6/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/37579/6/src/soc/intel/tigerlake/rom... PS6, Line 43:
What I meant is that at the time you pushed this, the whole soc/intel/tigerlake […]
Good to know. Thank you :)