Attention is currently required from: Cliff Huang, Subrata Banik.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ......................................................................
Patch Set 13:
(11 comments)
This change is ready for review.
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/1c279fc7_f8cdc6aa?usp... : PS12, Line 2:
we need below Kconfigs […]
Ack, added.
https://review.coreboot.org/c/coreboot/+/83798/comment/001f3a4a_2ec47d17?usp... : PS12, Line 17: select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
why we need this ?
Not needed. Removed.
https://review.coreboot.org/c/coreboot/+/83798/comment/87617bfc_f2f76903?usp... : PS12, Line 19: select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
look at line #23
Acknowledged
https://review.coreboot.org/c/coreboot/+/83798/comment/44b33284_a47367a3?usp... : PS12, Line 39: select MICROCODE_BLOB_UNDISCLOSED
look at line #35
Acknowledged
https://review.coreboot.org/c/coreboot/+/83798/comment/9c479a82_57277262?usp... : PS12, Line 43: select REG_SCRIPT
why you are selecting this ?
Ack, not required, removed.
https://review.coreboot.org/c/coreboot/+/83798/comment/db7177ff_48a5091c?usp... : PS12, Line 81: select SOC_INTEL_COMMON_BLOCK_USB4 : select SOC_INTEL_COMMON_BLOCK_USB4_PCIE : select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
use something like this because there are few design in past that doesn't have TCSS like chromebase […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83798/comment/7642471e_154f3bf8?usp... : PS12, Line 204: default 12
should be 10 for SOC_INTEL_PANTHERLAKE_U_H.
Acknowledged
https://review.coreboot.org/c/coreboot/+/83798/comment/6c2b9a11_2ad5c418?usp... : PS12, Line 368: config SOC_INTEL_CRASHLOG : def_bool n : select SOC_INTEL_COMMON_BLOCK_CRASHLOG : select ACPI_BERT : help : Enables CrashLog.
drop this as you know it exists anyway. https://github. […]
Ack, removed.
File src/soc/intel/pantherlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/2e9076bf_7ae64fc7?usp... : PS4, Line 11: { .slot = PCI_DEV_SLOT_PCIE_2, .count = 4, .lcap_port_base = 1 },
count should be 2, for rp9 and rp10.
Sure, updated to use count 2.
File src/soc/intel/pantherlake/xhci.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/1227e5b2_ad3052a4?usp... : PS12, Line 9: #define XHCI_USB2_PORT_NUM 10
should be 8 for PLT U_H […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83798/comment/acf3e284_ee1b1e66?usp... : PS12, Line 10: #define XHCI_USB3_PORT_NUM 4
use CONFIG_SOC_INTEL_USB3_DEV_MAX
Acknowledged