Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61681 )
Change subject: soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODO ......................................................................
soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODO
Sabrina uses the same MMIO_CONF_BASE MSR as the previous AMD CPUs to configure the PCI MMCONF base address.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61681 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 43c96c0..239a0e8 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -59,7 +59,7 @@ select SOC_AMD_COMMON_BLOCK_MCAX # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_NONCAR # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct - select SOC_AMD_COMMON_BLOCK_PCI_MMCONF # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct