Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM

[Marshall Dawson (Code Review)]

Hello Edward O'Callaghan, Julius Werner, Richard Spiegel, build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33759

to look at the new patch set (#15).

Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
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soc/amd/picasso: Create a hybrid romstage to begin in DRAM

Add the support files to begin execution in romstage and located in
DRAM.  Details for this implementation are found in
Documentation/amd/picasso/family17.md.

Combine steps typically found in bootblock, containing the reset
vector and protected mode enable, with the parts of romstage
that enable the console and cbmem.

Duplicate the ROMSTAGE_ADDR symbol into Kconfig and give it a safe
default value in DRAM.  Define EARLYRAM values for stack and early
storage prior to cbmem.  (A subsequent patch to add an FSP driver
will rely on the storage.)

Remove all postcar support.

This implementation assumes only a BSP will run the main romstage
code.  A subsequent change will add restrictions on APs, as AGESA
is put in place to release them from reset.

Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/Makefile.inc
M src/soc/amd/picasso/include/soc/cpu.h
M src/soc/amd/picasso/include/soc/romstage.h
M src/soc/amd/picasso/romstage.c
5 files changed, 107 insertions(+), 81 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33759/15