Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19360 )
Change subject: nb/amd/amdk8: Link reset_test.c ......................................................................
nb/amd/amdk8: Link reset_test.c
This needs some extra headers in amdk8/raminit.c that were otherwise provided by that file.
Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/19360 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi pgeorgi@google.com --- M src/cpu/amd/model_fxx/init_cpus.c M src/mainboard/amd/dbm690t/romstage.c M src/mainboard/amd/mahogany/romstage.c M src/mainboard/amd/pistachio/romstage.c M src/mainboard/amd/serengeti_cheetah/romstage.c M src/mainboard/asrock/939a785gmh/romstage.c M src/mainboard/asus/a8n_e/romstage.c M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/asus/k8v-x/romstage.c M src/mainboard/asus/kfsn4-dre_k8/romstage.c M src/mainboard/asus/m2n-e/romstage.c M src/mainboard/asus/m2v-mx_se/romstage.c M src/mainboard/asus/m2v/romstage.c M src/mainboard/broadcom/blast/romstage.c M src/mainboard/gigabyte/ga_2761gxdk/romstage.c M src/mainboard/gigabyte/m57sli/romstage.c M src/mainboard/hp/dl145_g1/romstage.c M src/mainboard/hp/dl145_g3/romstage.c M src/mainboard/iwill/dk8_htx/romstage.c M src/mainboard/kontron/kt690/romstage.c M src/mainboard/msi/ms7135/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9185/romstage.c M src/mainboard/msi/ms9282/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c M src/mainboard/siemens/sitemp_g1p1/romstage.c M src/mainboard/sunw/ultra40/romstage.c M src/mainboard/sunw/ultra40m2/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/technexion/tim5690/romstage.c M src/mainboard/technexion/tim8690/romstage.c M src/mainboard/tyan/s2912/romstage.c M src/mainboard/winent/mb6047/romstage.c M src/northbridge/amd/amdk8/Makefile.inc M src/northbridge/amd/amdk8/amdk8.h M src/northbridge/amd/amdk8/raminit.c M src/northbridge/amd/amdk8/reset_test.c 39 files changed, 21 insertions(+), 43 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 572ef99..035453e 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -11,6 +11,8 @@ * GNU General Public License for more details. */
+#include <cpu/x86/lapic.h> +#include <northbridge/amd/amdk8/amdk8.h> #include "cpu/amd/car/post_cache_as_ram.c"
#if CONFIG_HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 0e21475..3d42a64 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <spd.h> diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index b22dec1..8cec33c 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -26,7 +26,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 8578cd1..aaefe97 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <spd.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 9fac7cf..00c9a65 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -23,7 +23,6 @@ #include "southbridge/amd/amd8111/early_smbus.c" #include <reset.h> #include <northbridge/amd/amdk8/raminit.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> #include <delay.h>
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 1894fde..4067824 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -27,7 +27,6 @@ #include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index f58729d..59f9031 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -29,7 +29,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 04edc7e..9a286e5 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -33,7 +33,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index fb3bb57..b0704aa 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -33,7 +33,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 83194fc..e7ce151 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -33,7 +33,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83697hf/w83697hf.h> diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index c38164e..31478b4 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -32,7 +32,6 @@ #include "southbridge/nvidia/ck804/early_smbus.h" #include <reset.h> #include <northbridge/amd/amdk8/raminit.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> #include <delay.h>
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 7bf8306..69351ed 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -32,7 +32,6 @@ #include <lib.h> #include <spd.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 25eedba..8a79431 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -33,7 +33,6 @@ #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> -#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 3b6990b..aa67e37 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -33,7 +33,6 @@ #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> -#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index b618b52..7d92b57 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -12,7 +12,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 0414df1..b54740d 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -33,7 +33,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index c58b526..cdd6d43 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -30,7 +30,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 5420df1..3e800ba 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -15,7 +15,6 @@ #include <northbridge/amd/amdk8/amdk8.h> #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 6ccaf95..0570e6c 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -35,7 +35,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 9723ad2..76a5ee9 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -9,7 +9,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> #include <delay.h>
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 55ac1bc..54760d6 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -27,7 +27,6 @@ #include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 1da2ff4..142ff57 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -26,7 +26,6 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 35c8943..e961e0d 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -32,7 +32,6 @@ #include <lib.h> #include <spd.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 141c7e0..6d3b0a4 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -34,7 +34,6 @@ #include <delay.h> #include <reset.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index afb82eb..fbc362b 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -31,7 +31,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 9ae0ed4..c11d083 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -31,7 +31,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 4411368..169be6c 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -30,7 +30,6 @@ #include <delay.h>
#include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h>
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 7df486a..e43fc86 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -14,7 +14,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/smsc/lpc47b397/lpc47b397.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 576ca6b..5641adb 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -31,7 +31,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/smsc/dme1737/dme1737.h> #include <cpu/x86/bist.h>
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 60c3845..5316a84 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -28,7 +28,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index bc0a3ec..9f4a3bb 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -31,7 +31,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 4ffafb1..2c18148 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -26,7 +26,6 @@ #include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 7f41536..f04e805 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -26,7 +26,6 @@ #include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c"
#include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 97655aa..9bbd139 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -31,7 +31,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 327e592..c833c24 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -14,7 +14,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/x86/bist.h> diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc index fb2aca5..019f38e 100644 --- a/src/northbridge/amd/amdk8/Makefile.inc +++ b/src/northbridge/amd/amdk8/Makefile.inc @@ -11,6 +11,8 @@ romstage-y += raminit_f.c endif
+romstage-y += reset_test.c + # Enable this if you want to check the values of the PCI routing registers. # Call show_all_routes() anywhere amdk8.h is included. #ramstage-y += util.c diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 8c472ae..bc03b4c 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -11,12 +11,21 @@ #include "pre_f.h" #endif
+#define HTIC_ColdR_Detect (1<<4) +#define HTIC_BIOSR_Detect (1<<5) +#define HTIC_INIT_Detect (1<<6) + #ifdef __PRE_RAM__ void showallroutes(int level, pci_devfn_t dev); void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base); void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); #endif
+void set_bios_reset(void); +void distinguish_cpu_resets(unsigned int nodeid); +unsigned int get_sblk(void); +unsigned int get_sbbusn(unsigned sblk); + void cpus_ready_for_init(void);
#endif /* AMDK8_H */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 168f7ce..43229ea 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -5,7 +5,9 @@ */
#include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <lib.h> #include <stdlib.h> diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index f998c48..0d30016 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -1,10 +1,8 @@ +#include <arch/io.h> +#include <console/console.h> #include <stdint.h> #include <cpu/x86/lapic.h> -#include "raminit.h" - -#define HTIC_ColdR_Detect (1<<4) -#define HTIC_BIOSR_Detect (1<<5) -#define HTIC_INIT_Detect (1<<6) +#include "amdk8.h"
static inline int cpu_init_detected(unsigned nodeid) { @@ -33,7 +31,7 @@ return !(htic & HTIC_ColdR_Detect); }
-static inline void distinguish_cpu_resets(unsigned nodeid) +void distinguish_cpu_resets(unsigned int nodeid) { u32 htic; pci_devfn_t device; @@ -43,7 +41,6 @@ pci_io_write_config32(device, HT_INIT_CONTROL, htic); }
-void set_bios_reset(void); void set_bios_reset(void) { u32 htic; @@ -71,7 +68,7 @@ return 0; }
-static inline unsigned get_sblk(void) +unsigned int get_sblk(void) { u32 reg; /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ @@ -79,7 +76,7 @@ return ((reg>>8) & 3); }
-static inline unsigned get_sbbusn(unsigned sblk) +unsigned int get_sbbusn(unsigned sblk) { return node_link_to_bus(0, sblk); }
-
Martin Roth (Code Review)