New patch to review for coreboot: soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not needed

[Andrey Petrov]

Andrey Petrov ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15494

-gerrit

commit 204eaca6c6f48a032d0d9f3bed5a60b683c56b98
Author: Andrey Petrov 
Date:   Tue Jun 28 17:37:09 2016 -0700

soc/intel/apollolake: Let CSE know Ring Buffer Protocol is not needed

On Apollolake CSE can be used to fetch firmware from boot media. However,
    when this feature is not used, CSE needs to be explicitly notified of it
    before memory training is complete. This way it can transition to next
    state.

BUG=chrome-os-partner:53876
    TEST=CSE can be power-gated during S0iX. Confirmed with LTB.

Change-Id: I5141bff350b6c0bb662424b7b709f0787ec5fd28
    Signed-off-by: Andrey Petrov 
---
 src/soc/intel/apollolake/romstage.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index ce28326..0c093a4 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -241,6 +241,14 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
    	} else
    		printk(BIOS_DEBUG, "MRC cache was not found\n");
    }
+
+	/*
+	 * Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch
+	 * firmware for us, because we will do it on our own (SPI currently).
+	 * will let CSE state machine transition to next boot state, so that
+	 * it can function as designed.
+	 */
+	mupd->FspmConfig.SkipCseRbp = 1;
 }

__attribute__ ((weak))