Change in coreboot[master]: mb/google/zork: Move GPIO_137 configuration to ramstage

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43223 )

Change subject: mb/google/zork: Move GPIO_137 configuration to ramstage
......................................................................

mb/google/zork: Move GPIO_137 configuration to ramstage

This change moves the configuration of GPIO_137 to happen in ramstage
since there is nothing in coreboot that requires the state of write
protect GPIO for zork.

Change-Id: Ibaf8e7d9dd5d13a9b39b10ac0174de345b8380f5
Signed-off-by: Furquan Shaikh 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
2 files changed, 4 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/43223/1

diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index ea85819..8e6124c 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -28,8 +28,6 @@
    PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
    /* CLK_REQ2_L - NVMe */
    PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
    /* USI_RESET - reset */
    PAD_GPO(GPIO_140, HIGH),
    /* USB_HUB_RST_L - reset*/
@@ -57,8 +55,6 @@
    PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
    /* CLK_REQ2_L - NVMe */
    PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
    /* USI_RESET - reset */
    PAD_GPO(GPIO_140, HIGH),
    /* USB_HUB_RST_L - reset*/
@@ -165,6 +161,8 @@
    PAD_GPI(GPIO_132, PULL_NONE),
    /* DEV_BEEP_CODEC_IN (Dev beep Data out) */
    PAD_GPI(GPIO_135, PULL_NONE),
+	/* BIOS_FLASH_WP_ODL */
+	PAD_GPI(GPIO_137, PULL_NONE),
    /* DEV_BEEP_BCLK */
    PAD_GPI(GPIO_139, PULL_NONE),
    /* USI_RESET */
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index 60f997d..77a3212d 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -26,8 +26,6 @@
    PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
    /* CLK_REQ4_L - SSD */
    PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
    /* USI_RESET - reset */
    PAD_GPO(GPIO_140, HIGH),
    /* SD_AUX_RESET_L */
@@ -51,8 +49,6 @@
    PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
    /* CLK_REQ4_L - SSD */
    PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
    /* USI_RESET - reset */
    PAD_GPO(GPIO_140, HIGH),
    /* SD_AUX_RESET_L */
@@ -157,6 +153,8 @@
    PAD_GPI(GPIO_130, PULL_UP),
    /* DEV_BEEP_CODEC_IN (Dev beep Data out) */
    PAD_GPI(GPIO_135, PULL_NONE),
+	/* BIOS_FLASH_WP_ODL */
+	PAD_GPI(GPIO_137, PULL_NONE),
    /* DEV_BEEP_BCLK */
    PAD_GPI(GPIO_139, PULL_NONE),
    /* USI_RESET */

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43223 )

Change subject: mb/google/zork: Move GPIO_137 configuration to ramstage
......................................................................

Patch Set 1: Code-Review+2

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43223 )

Change subject: mb/google/zork: Move GPIO_137 configuration to ramstage
......................................................................

Patch Set 1: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43223 )

Change subject: mb/google/zork: Move GPIO_137 configuration to ramstage
......................................................................

mb/google/zork: Move GPIO_137 configuration to ramstage

This change moves the configuration of GPIO_137 to happen in ramstage
since there is nothing in coreboot that requires the state of write
protect GPIO for zork.

Change-Id: Ibaf8e7d9dd5d13a9b39b10ac0174de345b8380f5
Signed-off-by: Furquan Shaikh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43223
Reviewed-by: Aaron Durbin 
Reviewed-by: Raul Rangel 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
2 files changed, 4 insertions(+), 8 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Raul Rangel: Looks good to me, approved

diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index ea85819..8e6124c 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -28,8 +28,6 @@
    PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
    /* CLK_REQ2_L - NVMe */
    PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
    /* USI_RESET - reset */
    PAD_GPO(GPIO_140, HIGH),
    /* USB_HUB_RST_L - reset*/
@@ -57,8 +55,6 @@
    PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
    /* CLK_REQ2_L - NVMe */
    PAD_NF(GPIO_116, CLK_REQ2_L, PULL_UP),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
    /* USI_RESET - reset */
    PAD_GPO(GPIO_140, HIGH),
    /* USB_HUB_RST_L - reset*/
@@ -165,6 +161,8 @@
    PAD_GPI(GPIO_132, PULL_NONE),
    /* DEV_BEEP_CODEC_IN (Dev beep Data out) */
    PAD_GPI(GPIO_135, PULL_NONE),
+	/* BIOS_FLASH_WP_ODL */
+	PAD_GPI(GPIO_137, PULL_NONE),
    /* DEV_BEEP_BCLK */
    PAD_GPI(GPIO_139, PULL_NONE),
    /* USI_RESET */
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
index 60f997d..77a3212d 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c
@@ -26,8 +26,6 @@
    PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
    /* CLK_REQ4_L - SSD */
    PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
    /* USI_RESET - reset */
    PAD_GPO(GPIO_140, HIGH),
    /* SD_AUX_RESET_L */
@@ -51,8 +49,6 @@
    PAD_NF(GPIO_115, CLK_REQ1_L, PULL_UP),
    /* CLK_REQ4_L - SSD */
    PAD_NF(GPIO_132, CLK_REQ4_L, PULL_UP),
-	/* BIOS_FLASH_WP_ODL */
-	PAD_GPI(GPIO_137, PULL_NONE),
    /* USI_RESET - reset */
    PAD_GPO(GPIO_140, HIGH),
    /* SD_AUX_RESET_L */
@@ -157,6 +153,8 @@
    PAD_GPI(GPIO_130, PULL_UP),
    /* DEV_BEEP_CODEC_IN (Dev beep Data out) */
    PAD_GPI(GPIO_135, PULL_NONE),
+	/* BIOS_FLASH_WP_ODL */
+	PAD_GPI(GPIO_137, PULL_NONE),
    /* DEV_BEEP_BCLK */
    PAD_GPI(GPIO_139, PULL_NONE),
    /* USI_RESET */