Dan Elkouby has uploaded this change for review. ( https://review.coreboot.org/25662
Change subject: mb/asus/p8z77-v_pro: Add ASUS P8Z77-V Pro ......................................................................
mb/asus/p8z77-v_pro: Add ASUS P8Z77-V Pro
Working: - S3 - USB - GBE - PCIe - PCIe graphics - All SATA ports - HWM (PECI missing) - Native memory init with XMP - flashrom with the internal programmer, vendor firmware locks the BIOS region
Untested: - EHCI debug - PCIe 1x slots, probably need enabling - The PCIe 4x slot from the southbridge shares lanes with some of the ASMedia chips on this board, and defaults to 1x or 2x mode, 4x mode untested - WiFi, I don't have the module installed - Onboard audio, mine is partially broken but it shows up in Linux - PCIe to PCI bridge, shows up in Linux but not tested - PS/2, enabled in devicetree but untested
Not working: - Integrated graphics - Blinking the front panel LED in S3 - ASM1042 "charging mode" for 1A USB power
Change-Id: I10baf73a848576a0ce7e18c6b36bcd605f80b211 Signed-off-by: Dan Elkouby streetwalkermc@gmail.com --- A src/mainboard/asus/p8z77-v_pro/Kconfig A src/mainboard/asus/p8z77-v_pro/Kconfig.name A src/mainboard/asus/p8z77-v_pro/Makefile.inc A src/mainboard/asus/p8z77-v_pro/acpi/ec.asl A src/mainboard/asus/p8z77-v_pro/acpi/platform.asl A src/mainboard/asus/p8z77-v_pro/acpi/superio.asl A src/mainboard/asus/p8z77-v_pro/acpi_tables.c A src/mainboard/asus/p8z77-v_pro/board_info.txt A src/mainboard/asus/p8z77-v_pro/devicetree.cb A src/mainboard/asus/p8z77-v_pro/dsdt.asl A src/mainboard/asus/p8z77-v_pro/gpio.c A src/mainboard/asus/p8z77-v_pro/hda_verb.c A src/mainboard/asus/p8z77-v_pro/mainboard.c A src/mainboard/asus/p8z77-v_pro/romstage.c 14 files changed, 830 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/25662/1
diff --git a/src/mainboard/asus/p8z77-v_pro/Kconfig b/src/mainboard/asus/p8z77-v_pro/Kconfig new file mode 100644 index 0000000..543e15a --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/Kconfig @@ -0,0 +1,73 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Dan Elkouby streetwalkermc@gmail.com +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8Z77_V_PRO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_LGA1155 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + select SUPERIO_NUVOTON_NCT6779D + select DRIVERS_ASMEDIA_ASPM_BLACKLIST + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default asus/p8z77-v_pro + +config MAINBOARD_PART_NUMBER + string + default "P8Z77-V Pro" + +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config VGA_BIOS_ID + string + default "8086,0162" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x84ca + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: EHCI debug untested + int + default 2 +endif diff --git a/src/mainboard/asus/p8z77-v_pro/Kconfig.name b/src/mainboard/asus/p8z77-v_pro/Kconfig.name new file mode 100644 index 0000000..798ddb6 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_P8Z77_V_PRO + bool "P8Z77-V Pro" diff --git a/src/mainboard/asus/p8z77-v_pro/Makefile.inc b/src/mainboard/asus/p8z77-v_pro/Makefile.inc new file mode 100644 index 0000000..0fd85ed --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Dan Elkouby streetwalkermc@gmail.com +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c diff --git a/src/mainboard/asus/p8z77-v_pro/acpi/ec.asl b/src/mainboard/asus/p8z77-v_pro/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/acpi/ec.asl diff --git a/src/mainboard/asus/p8z77-v_pro/acpi/platform.asl b/src/mainboard/asus/p8z77-v_pro/acpi/platform.asl new file mode 100644 index 0000000..2dc7e6e --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby streetwalkermc@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asus/p8z77-v_pro/acpi/superio.asl b/src/mainboard/asus/p8z77-v_pro/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/acpi/superio.asl diff --git a/src/mainboard/asus/p8z77-v_pro/acpi_tables.c b/src/mainboard/asus/p8z77-v_pro/acpi_tables.c new file mode 100644 index 0000000..345177f --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby streetwalkermc@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asus/p8z77-v_pro/board_info.txt b/src/mainboard/asus/p8z77-v_pro/board_info.txt new file mode 100644 index 0000000..32f7a9e --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/board_info.txt @@ -0,0 +1,9 @@ +Category: desktop +Vendor name: ASUS +Board name: P8Z77-V Pro +ROM package: DIP8 +ROM socketed: y +ROM protocol: SPI +Flashrom support: y +Release year: 2012 + diff --git a/src/mainboard/asus/p8z77-v_pro/devicetree.cb b/src/mainboard/asus/p8z77-v_pro/devicetree.cb new file mode 100644 index 0000000..c6747f4 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/devicetree.cb @@ -0,0 +1,175 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Dan Elkouby streetwalkermc@gmail.com +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_LGA1155 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 1, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1043 0x84ca + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1043 0x84ca + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1043 0x849c + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1043 0x84ca + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1043 0x84fb + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1043 0x84ca + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x1043 0x84ca + end + device pci 1c.3 on # PCIe Port #4 + subsystemid 0x1043 0x84ca + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x1043 0x84ca + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 on # PCIe Port #8 + subsystemid 0x1043 0x84ca + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1043 0x84ca + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip superio/nuvoton/nct6779d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.9 off end # GPIO1-8 + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware Monitor, Front Panel LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO Push-pull/Open-drain selection + device pnp 2e.14 off end # PORT80 UART + device pnp 2e.16 off end # Deep Sleep + device pnp 2e.108 off end # GPIO0 + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on end # GPIO2 + device pnp 2e.309 on end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1043 0x84ca + end + device pci 1f.3 on # SMBus + subsystemid 0x1043 0x84ca + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1043 0x84ca + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x1043 0x84ca + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1043 0x84ca + end + device pci 01.1 on + subsystemid 0x1043 0x84ca + end + end +end diff --git a/src/mainboard/asus/p8z77-v_pro/dsdt.asl b/src/mainboard/asus/p8z77-v_pro/dsdt.asl new file mode 100644 index 0000000..ab31a0c --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/dsdt.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby streetwalkermc@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/asus/p8z77-v_pro/gpio.c b/src/mainboard/asus/p8z77-v_pro/gpio.c new file mode 100644 index 0000000..01356e6 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/gpio.c @@ -0,0 +1,195 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby streetwalkermc@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8z77-v_pro/hda_verb.c b/src/mainboard/asus/p8z77-v_pro/hda_verb.c new file mode 100644 index 0000000..6ac44eb --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/hda_verb.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby streetwalkermc@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x104384fb, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x104384fb), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x99430140), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x01011012), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x01012014), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19850), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c60), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181305f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x01456130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8z77-v_pro/mainboard.c b/src/mainboard/asus/p8z77-v_pro/mainboard.c new file mode 100644 index 0000000..14a056c --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby streetwalkermc@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(device_t dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/p8z77-v_pro/romstage.c b/src/mainboard/asus/p8z77-v_pro/romstage.c new file mode 100644 index 0000000..3c85804 --- /dev/null +++ b/src/mainboard/asus/p8z77-v_pro/romstage.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Dan Elkouby streetwalkermc@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define SIO_PORT 0x2e +#define SIO_DEV PNP_DEV(SIO_PORT, 0) +#define GPIO_PPOD_DEV PNP_DEV(SIO_PORT, NCT6779D_GPIO_PP_OD) +#define ACPI_DEV PNP_DEV(SIO_PORT, NCT6779D_ACPI) +#define HWM_DEV PNP_DEV(SIO_PORT, NCT6779D_HWM_FPLED) +#define GPIO_DEV PNP_DEV(SIO_PORT, NCT6779D_GPIO12345678_V) +#define GPIO01_DEV PNP_DEV(SIO_PORT, NCT6779D_WDT1_GPIO01_V) + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 2, 0 }, + { 1, 2, 0 }, + { 1, 2, 1 }, + { 1, 2, 1 }, + { 1, 2, 2 }, + { 1, 2, 2 }, + { 1, 2, 3 }, + { 1, 2, 3 }, + { 1, 2, 4 }, + { 1, 2, 4 }, + { 1, 2, 6 }, + { 1, 2, 5 }, + { 1, 2, 5 }, + { 1, 2, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(SIO_DEV); + + /* Pin function selection */ + pnp_write_config(SIO_DEV, 0x1a, 0x00); + pnp_write_config(SIO_DEV, 0x2a, 0x40); + pnp_write_config(SIO_DEV, 0x2c, 0x00); + + pnp_set_logical_device(GPIO_PPOD_DEV); + pnp_write_config(SIO_DEV, 0xe4, 0xfc); + pnp_write_config(SIO_DEV, 0xe6, 0x7f); + + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(SIO_DEV, 0xe2, 0x76); + + /* Power RAM in S3 */ + pnp_write_config(SIO_DEV, 0xe4, 0x10); + + pnp_set_logical_device(HWM_DEV); + pnp_write_config(SIO_DEV, 0xe2, 0x7f); + pnp_write_config(SIO_DEV, 0xe4, 0xf1); + pnp_write_config(SIO_DEV, 0xf0, 0x3e); + + pnp_set_logical_device(GPIO_DEV); + pnp_write_config(SIO_DEV, 0x30, 0x2e); + + /* GPIO2 */ + pnp_write_config(SIO_DEV, 0xe0, 0xdf); + pnp_write_config(SIO_DEV, 0xe2, 0x00); + pnp_write_config(SIO_DEV, 0xe9, 0x00); + pnp_write_config(SIO_DEV, 0xe1, 0xc0); + + /* GPIO3 */ + pnp_write_config(SIO_DEV, 0xe4, 0x7f); + pnp_write_config(SIO_DEV, 0xe6, 0x00); + pnp_write_config(SIO_DEV, 0xea, 0x00); + pnp_write_config(SIO_DEV, 0xe5, 0x70); + + /* GPIO5 */ + pnp_write_config(SIO_DEV, 0xf4, 0xfc); + pnp_write_config(SIO_DEV, 0xf6, 0x00); + pnp_write_config(SIO_DEV, 0xeb, 0x00); + pnp_write_config(SIO_DEV, 0xf5, 0x88); + + pnp_set_logical_device(GPIO01_DEV); + + /* GPIO1 */ + pnp_write_config(SIO_DEV, 0xf0, 0x7f); + pnp_write_config(SIO_DEV, 0xf2, 0x00); + pnp_write_config(SIO_DEV, 0xf4, 0x00); + pnp_write_config(SIO_DEV, 0xf1, 0x03); + + nuvoton_pnp_exit_conf_state(SIO_DEV); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +}