Change in coreboot[master]: mb/intel/adlrvp: Add support for external clock buffer

[Paul Menzel (Code Review)]

Attention is currently required from: V Sowmya, Subrata Banik, Maulik V Vaghela, Angel Pons, Tim Wawrzynczak.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59976 )

Change subject: mb/intel/adlrvp: Add support for external clock buffer
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Patch Set 10:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/59976/comment/593985b9_cab84174 
PS10, Line 9: ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals.
            : Out of 7 SRCCLK's 3 will be used for CPU, the rest are for PCH.
            : If more than 4 PCH devices are connected on the platform, an external
            : differential buffer chip needs to be placed at the platform level.
Please reflow for 75 characters per line. (Whole message.)

File src/mainboard/intel/adlrvp/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/59976/comment/e1fff69c_5902bd1d 
PS10, Line 41: int
unsigned