Change in coreboot[master]: mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMe

[Kevin Chiu (Code Review)]

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58135 )

Change subject: mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMe
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mb/google/guybrush/var/nipperkin: Enable RTD3 support for eMMC as NVMe

nipperkin has different H/W topology to guybrush that the eMMC device
is on a different GPP:
guybrush: GPP3
nipperkin: GPP2

Hence we need to enable RTD3 for nipperkin additionally which refers
to this one:
https://review.coreboot.org/c/coreboot/+/54967

BUG=b:200246826
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
     run suspend test on eMMC sku

Signed-off-by: Kevin Chiu 
Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9
---
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/58135/1

diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
index ecaf0cd..a53a6e5 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
@@ -32,6 +32,13 @@

chip soc/amd/cezanne
    device domain 0 on
+		device ref gpp_bridge_2 on
+			# Required so the NVMe gets placed into D3 when entering S0i3.
+			chip drivers/pcie/rtd3/device
+				register "name" = ""NVME""
+				device pci 00.0 on end
+			end
+		end # NVMe
    	device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
    		device ref acp on
    			chip drivers/amd/i2s_machine_dev