Attention is currently required from: David Wu, Zhuohao Lee, Alan Huang.
Hou-hsun Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59576 )
Change subject: mb/google/brya/var/brask: Set PL and PsysPL
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/brask/ramstage.c:
https://review.coreboot.org/c/coreboot/+/59576/comment/0bc4edec_26317fa1
PS1, Line 18: { PCI_DEVICE_ID_INTEL_ADL_P_ID_1, 45, 5000, 45000, 80000, 80000, 159000 },
Yes, you're correct.
Done
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