Tom Hiller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Intel GBE 82579LM bincfg set and spec
Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963 Signed-off-by: Tom Hiller thrilleratplay@gmail.com --- M util/bincfg/Makefile A util/bincfg/gbe-82579LM.set A util/bincfg/gbe-82579LM.spec 3 files changed, 451 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44510/1
diff --git a/util/bincfg/Makefile b/util/bincfg/Makefile index 1b3e936..b35cd3e 100644 --- a/util/bincfg/Makefile +++ b/util/bincfg/Makefile @@ -19,6 +19,13 @@ cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin rm -f gbe1.bin
+# Use this target to generate GbE for X200 +gen-gbe-82579LM: + ./bincfg gbe-82579LM.spec gbe-82579LM.set gbe1.bin + # duplicate binary as per spec + cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin + rm -f gbe1.bin + # Use this target to generate IFD for X200 gen-ifd-x200: ./bincfg ifd-x200.spec ifd-x200.set flashregion_0_fd.bin diff --git a/util/bincfg/gbe-82579LM.set b/util/bincfg/gbe-82579LM.set new file mode 100644 index 0000000..01ae470 --- /dev/null +++ b/util/bincfg/gbe-82579LM.set @@ -0,0 +1,288 @@ +# SPDX-License-Identifier: GPL-3.0-or-later + +# +# Datasheets: +# +# https://cdrdv2.intel.com/v1/dl/getContent/613456 + +# The datasheet says that this spec covers the following pci ids: +# 8086:1502 - Intel 82579LM gigabit ethernet controller +# 8086:1503 - Intel 82579V gigabit ethernet controller + +# Naming convention +# * Word groups separated by a blank line +# * Word groups with known meaning given a prefix +# * prefix will be defined in comment before group +# * Variable names to be named using a prefix, descriptive name and bit offset +# within the word, separated by an underscore. +# * Example: "prefix_description_0" +# * Unidentified reserved word groups will be named reserved and LAN Word +# * EXCEPTION: Word 0x24, Word 0x25, Word 0x26 also include bit offset +# within the word +# Offset hex address, separated by an underscore. +# * Example: "reserved_x03" +# * Nonprefixed names will be named reserved and LAN Word Offset hex address, +# separated by an underscore. +# * Example: "imageversioninfo_x05" +# * Unspecified words are prefixed with "offset_" + +# GbE values for 82579LM +{ + # This example sets MAC address to 00:DE:AD:C0:FF:EE + # USE YOUR DEVICES MAC ADDRESS!! + # prefix: "mac_" + "mac_address_0" = 0x00, + "mac_address_1" = 0xDE, + "mac_address_2" = 0xAD, + "mac_address_3" = 0xC0, + "mac_address_4" = 0xFF, + "mac_address_5" = 0xEE, + + # Reserved (Word 0x3) + "reserved_x03" = 0x0800, + + # Reserved (Word 0x04) + "reserved_x04" = 0xffff, + + # Image Version Information (Word 0x05) + "imageversioninfo_x05" = 0x00D3, + + "reserved_x06" = 0xffff, + "reserved_x07" = 0xffff, + + # PBA Low and PBA High (Words 0x08 and 0x09) + # prefix: "pba_" + "pba_low_x08" = 0xffff, + "pba_high_x09" = 0xffff, + + # PCI Init Control Word (Word 0x0A) + # prefix: "pci_" + "pci_loaddeviceid_0" = 1, + "pci_loadsubsystemid_1" = 1, + "pci_reserved_2" = 0, + "pci_reserved_3" = 0x0, + "pci_pmenable_6" = 1, + "pci_auxpwr_7" = 1, + "pci_reserved_8" = 0x10, + + # ************* Configurable PCI IDs **************** + # TODO: make command line switch for these + # Subsystem ID (Word 0x0B) + "subsystemid_x0B" = 0, + # Subsystem Vendor ID (Word 0x0C) + "subsystemvendorid_x0C" = 0x8086, + # Device ID (Word 0x0D) + # TODO: 82579V uses "deviceid_x0D" = 0x1503, + "deviceid_x0D" = 0x1502, + # ************* END Configurable PCI IDs **************** + + # Words 0x0E and 0x0F Are Reserved + "reserved_x0E" = 0x0, + "reserved_x0F" = 0x0, + + # LAN Power Consumption (Word 0x10) + # prefix: "lanpwr_" + "lanpwr_d3pwr_0" = 0x2, + "lanpwr_reserved_5" = 0, + "lanpwr_d0pwr_8" = 0x7, + + # Word 0x12 and Word 0x11 Are Reserved + "reserved_x11" = 0x0000, + "reserved_x12" = 0x0000, + + # Shared Init Control Word (Word 0x13) + # prefix: "sicw_" + "sicw_dynamicclock_0" = 1, + "sicw_clkcnt_1" = 0, + "sicw_reserved_2" = 1, + "sicw_fullduplex_3" = 0, + "sicw_forcespeed_4" = 0, + "sicw_reserved_5" = 0, + "sicw_phydeviceype_6" = 0, + "sicw_reserved_8" = 1, + "sicw_phy_enpwrdown_9" = 0, + "sicw_reserved_10" = 1, + "sicw_macsecdisable_13" = 1, + "sicw_sign_14" = 0x2, + + # Extended Configuration Word 1 (Word 0x14) + # prefix: "ecw1_" + "ecw1_extcfgptr_0" = 0x0028, + "ecw1_oemload_12" = 1, + "ecw1_phyload_13" = 1, + "ecw1_reserved_14" = 0, + + # Extended Configuration Word 2 (Word 0x15) + # prefix: "ecw2_" + "ecw2_reserved_0" = 0x00, + "ecw2_extphylen_8" = 0x12, + + # Extended Configuration Word 3 (Word 0x16) + # prefix: "ecw3_" + "ecw3_extcfg1_0" = 0x00, + + # OEM Configuration Defaults (Word 0x17) + # prefix: "oem_" + "oem_reserved_0" = 0x000, + "oem_lpluenind0a_9" = 0, + "oem_lplueninnond0a_10" = 1, + "oem_gbedisinnond0a_11" = 1, + "oem_reserved_12" = 0, + "oem_gbedis_14" = 0, + "oem_reserved_15" = 0, + + # LED 0 - 2 Configuration Defaults (Word 0x18) + # prefix: "l02_" + # Lenovo default values + "l02_led0mode_0" = 0x4, + "l02_led0invert_3" = 0, + "l02_led0blink_4" = 0, + "l02_led1mode_5" = 0x3, + "l02_led1invert_8" = 0, + "l02_led1blink_9" = 1, + "l02_led2mode_10" = 0x2, + "l02_led2invert_13" = 1, + "l02_led2blink_14" = 0, + "l02_blinkrate_15" = 0, + + # Intel default Values + #"l02_led0mode_0" = 0x4, + #"l02_led0invert_3" = 0, + #"l02_led0blink_4" = 1, + #"l02_led1mode_5" = 0x7, + #"l02_led1invert_8" = 0, + #"l02_led1blink_9" = 0, + #"l02_led2mode_10" = 0x6, + #"l02_led2invert_13" = 0, + #"l02_led2blink_14" = 0, + #"l02_blinkrate_15" = 0, + + + # Reserved (Word 0x19) + # NOTE: bit 6 must be 1 for validation. See datasheet. + "reserved_x19" = 0x2B40, + + # Reserved (Word 0x1A) + # Advanced Power Management Wake Up Enable + # prefix: "amp_" + "amp_enable_0" = 1, + "amp_reserved_1" = 0x0421, + + # Reserved (Word 0x1B) + "reserved_x1B" = 0x0113, + + # Reserved (Word 0x1C) + "reserved_x1C" = 0x1502, + + # Reserved (Word 0x1D) + "reserved_x1D" = 0xBAAD, + + # Reserved (Word 0x1E) + "reserved_x1E" = 0x1502, + + # Reserved (Word 0x1F) + "reserved_x1F" = 0x1503, + + # Reserved (Word 0x20) + "reserved_x20" = 0xBAAD, + + # Reserved (Word 0x21) + "reserved_x21" = 0xBAAD, + + # Reserved (Word 0x22) + "reserved_x22" = 0xBAAD, + + # Reserved (Word 0x23) + "reserved_x23" = 0x1502, + + # Reserved (Word 0x24) + "reserved_x24_0" = 0x0000, + "reserved_x24_14" = 0, + "reserved_x24_15" = 1, + + # Reserved (Word 0x25) + "reserved_x25_0" = 0x0000, + "reserved_x25_4" = 1, + "reserved_x25_5" = 0, + "reserved_x25_7" = 1, + "reserved_x25_8" = 0x00, + "reserved_x25_15" = 1, + + # Reserved (Word 0x26) + "reserved_x26_0" = 0x00, + "reserved_x26_9" = 1, + "reserved_x26_10" = 1, + "reserved_x26_11" = 1, + "reserved_x26_12" = 0, + "reserved_x26_14" = 1, + "reserved_x26_15" = 0, + + # Reserved (Word 0x27) + "reserved_x27" = 0x80, + + # Offsets 0x28-0x2F + "offset_x28" = 0x0000, + "offset_x29" = 0x0000, + "offset_x2A" = 0x0000, + "offset_x2B" = 0x0000, + "offset_x2C" = 0x0000, + "offset_x2D" = 0x0000, + "offset_x2E" = 0x0000, + "offset_x2F" = 0x0000, + + # Boot Agent Main Setup Options (Word 0x30) + # Hardcoded PXE setup (disabled) + # prefix: "pxe30_" + "pxe30_protocolsel_0" = 0, + "pxe30_reserved_2" = 0, + "pxe30_defbootsel_3" = 0x3, + "pxe30_reserved_5" = 0, + "pxe30_prompttime_6" = 0x3, + "pxe30_dispsetup_8" = 0, + "pxe30_reserved_9" = 0, + "pxe30_forcespeed_10" = 0, + "pxe30_forcefullduplex_12" = 0, + "pxe30_reserved_13" = 0, + "pxe30_reserved_14" = 0, + + # Boot Agent Configuration Customization Options (Word 0x31) + # prefix: "pxe31_" + "pxe31_disablemenu_0" = 1, + "pxe31_disabletitle_1" = 1, + "pxe31_disableprotsel_2" = 0, + "pxe31_disbootorder_3" = 0, + "pxe31_dislegacywak_4" = 0, + "pxe31_disableflasicwpro_5" = 0, + "pxe31_reserved_6" = 0, + "pxe31_ibootagentmode_8" = 0, + "pxe31_contretrydis_11" = 0, + "pxe31_reserved_12" = 0, + "pxe31_signature_14" = 10, + + # Boot Agent Configuration Customization Options (Word 0x32) + # prefix: "pxe32_" + "pxe32_buildnum_0" = 0x28, + "pxe32_minorversion_8" = 0x2, + "pxe32_majorversion_12" = 0x1, + + # IBA Capabilities (Word 0x33) + # prefix: "pxe33_" + "pxe33_basecodepresent_0" = 1, + "pxe33_undipresent_1" = 1, + "pxe33_reserved_2" = 1, + "pxe33_efiundipresent_3" = 0, + "pxe33_iscsi_4" = 0, + "pxe33_reserved_5" = 0, + "pxe33_signature_14" = 10, + + "pxe_padding"[11] = 0xffff, + + # Checksum is generated by bincfg + # "checksum_gbe" = xxx, + + # G3 -> S5 PHY Configuration + "g3_s5_phy_conf"[0x16] = 0, + + # Padding 0xf80 bytes + "padding"[0xf6a] = 0xff +} diff --git a/util/bincfg/gbe-82579LM.spec b/util/bincfg/gbe-82579LM.spec new file mode 100644 index 0000000..778d580 --- /dev/null +++ b/util/bincfg/gbe-82579LM.spec @@ -0,0 +1,156 @@ +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# +# Datasheets: +# +# https://cdrdv2.intel.com/v1/dl/getContent/613456 + +# The datasheet says that this spec covers the following pci ids: +# 8086:1502 - Intel 82579LM gigabit ethernet controller +# 8086:1503 - Intel 82579V gigabit ethernet controller + +# GbE SPEC for 82579LM/82579V +{ + "mac_address_"[6] : 8, + "reserved_x03" : 16, + "reserved_x04" : 16, + "imageversioninfo_x05" : 16, + "reserved_x06" : 16, + "reserved_x07" : 16, + "pba_low_x08" : 16, + "pba_high_x09" : 16, + "pci_loaddeviceid_0" : 1, + "pci_loadsubsystemid_1" : 1, + "pci_reserved_2" : 1, + "pci_reserved_3" : 3, + "pci_pmenable_6" : 1, + "pci_auxpwr_7" : 1, + "pci_reserved_8" : 8, + "subsystemid_x0B" : 16, + "subsystemvendorid_x0C" : 16, + "deviceid_x0D" : 16, + "reserved_x0E" : 16, + "reserved_x0F" : 16, + "lanpwr_d3pwr_0" : 5, + "lanpwr_reserved_5" : 3, + "lanpwr_d0pwr_8" : 8, + "reserved_x11" : 16, + "reserved_x12" : 16, + "sicw_dynamicclock_0" : 1, + "sicw_clkcnt_1" : 1, + "sicw_reserved_2" : 1, + "sicw_fullduplex_3" : 1, + "sicw_forcespeed_4" : 1, + "sicw_reserved_5" : 1, + "sicw_phydeviceype_6" : 2, + "sicw_reserved_8" : 1, + "sicw_phy_enpwrdown_9" : 1, + "sicw_reserved_10" : 3, + "sicw_macsecdisable_13" : 1, + "sicw_sign_14" : 2, + "ecw1_extcfgptr_0" : 12, + "ecw1_oemload_12" : 1, + "ecw1_phyload_13" : 1, + "ecw1_reserved_14" : 2, + "ecw2_reserved_0" : 8, + "ecw2_extphylen_8" : 8, + "ecw3_extcfg1_0" : 16, + "oem_reserved_0" : 9, + "oem_lpluenind0a_9" : 1, + "oem_lplueninnond0a_10" : 1, + "oem_gbedisinnond0a_11" : 1, + "oem_reserved_12" : 2, + "oem_gbedis_14" : 1, + "oem_reserved_15" : 1, + "l02_led0mode_0" : 3, + "l02_led0invert_3" : 1, + "l02_led0blink_4" : 1, + "l02_led1mode_5" : 3, + "l02_led1invert_8" : 1, + "l02_led1blink_9" : 1, + "l02_led2mode_10" : 3, + "l02_led2invert_13" : 1, + "l02_led2blink_14" : 1, + "l02_blinkrate_15" : 1, + "reserved_x19" : 16, + "amp_enable_0" : 1, + "amp_reserved_1" : 15, + "reserved_x1B" : 16, + "reserved_x1C" : 16, + "reserved_x1D" : 16, + "reserved_x1E" : 16, + "reserved_x1F" : 16, + "reserved_x20" : 16, + "reserved_x21" : 16, + "reserved_x22" : 16, + "reserved_x23" : 16, + "reserved_x24_0" : 14, + "reserved_x24_14" : 1, + "reserved_x24_15" : 1, + "reserved_x25_0" : 4, + "reserved_x25_4" : 1, + "reserved_x25_5" : 2, + "reserved_x25_7" : 1, + "reserved_x25_8" : 7, + "reserved_x25_15" : 1, + "reserved_x26_0" : 9, + "reserved_x26_9" : 1, + "reserved_x26_10" : 1, + "reserved_x26_11" : 1, + "reserved_x26_12" : 2, + "reserved_x26_14" : 1, + "reserved_x26_15" : 1, + "reserved_x27" : 16, + "offset_x28" : 16, + "offset_x29" : 16, + "offset_x2A" : 16, + "offset_x2B" : 16, + "offset_x2C" : 16, + "offset_x2D" : 16, + "offset_x2E" : 16, + "offset_x2F" : 16, + "pxe30_protocolsel_0" : 2, + "pxe30_reserved_2" : 1, + "pxe30_defbootsel_3" : 2, + "pxe30_reserved_5" : 1, + "pxe30_prompttime_6" : 2, + "pxe30_dispsetup_8" : 1, + "pxe30_reserved_9" : 1, + "pxe30_forcespeed_10" : 2, + "pxe30_forcefullduplex_12" : 1, + "pxe30_reserved_13" : 1, + "pxe30_reserved_14" : 2, + "pxe31_disablemenu_0" : 1, + "pxe31_disabletitle_1" : 1, + "pxe31_disableprotsel_2" : 1, + "pxe31_disbootorder_3" : 1, + "pxe31_dislegacywak_4" : 1, + "pxe31_disableflasicwpro_5" : 1, + "pxe31_reserved_6" : 2, + "pxe31_ibootagentmode_8" : 3, + "pxe31_contretrydis_11" : 1, + "pxe31_reserved_12" : 2, + "pxe31_signature_14" : 2, + "pxe32_buildnum_0" : 8, + "pxe32_minorversion_8" : 4, + "pxe32_majorversion_12" : 4, + "pxe33_basecodepresent_0" : 1, + "pxe33_undipresent_1" : 1, + "pxe33_reserved_2" : 1, + "pxe33_efiundipresent_3" : 1, + "pxe33_iscsi_4" : 1, + "pxe33_reserved_5" : 9, + "pxe33_signature_14" : 2, + "pxe_padding"[11] : 16, + "checksum_gbe" : 16, + "g3_s5_phy_conf"[0x16] : 8, + "padding"[0xf6a] : 8 +}
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44510
to look at the new patch set (#2).
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Intel GBE 82579LM bincfg set and spec
Using bincfg, generate Intel 82579LM GBE region firmware.
* Intel 82579LM is used in Lenovo models including x220 and x230. * PXE is disabled. * Intel 82579V variant could be generated with a few modifications to set. Noted in set file comments.
Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963 Signed-off-by: Tom Hiller thrilleratplay@gmail.com --- M util/bincfg/Makefile A util/bincfg/gbe-82579LM.set A util/bincfg/gbe-82579LM.spec 3 files changed, 451 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44510/2
Damien Zammit has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Looks pretty good to me, did you test this by comparing what it generated to your actual GbE? If it was identical, we can probably merge this, or if it wasn't identical did you test on hw?
https://review.coreboot.org/c/coreboot/+/44510/2/util/bincfg/Makefile File util/bincfg/Makefile:
https://review.coreboot.org/c/coreboot/+/44510/2/util/bincfg/Makefile@22 PS2, Line 22: # Use this target to generate GbE for X200 This should be X220/X230 instead of X200.
Hello build bot (Jenkins), Damien Zammit, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44510
to look at the new patch set (#3).
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Intel GBE 82579LM bincfg set and spec
Using bincfg, generate Intel 82579LM GBE region firmware.
* Intel 82579LM is used in Lenovo models including x220 and x230. * PXE is disabled. * Intel 82579V variant could be generated with a few modifications to set. Noted in set file comments.
Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963 Signed-off-by: Tom Hiller thrilleratplay@gmail.com --- M util/bincfg/Makefile A util/bincfg/gbe-82579LM.set A util/bincfg/gbe-82579LM.spec 3 files changed, 451 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44510/3
Tom Hiller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 3:
Patch Set 2: Code-Review+1
(1 comment)
Looks pretty good to me, did you test this by comparing what it generated to your actual GbE? If it was identical, we can probably merge this, or if it wasn't identical did you test on hw?
I tested it against the stock GBE and tested it on a X220. There are a few variations between this and the stock GBE, I used Intel defaults with the exception of the LEDs and disabling the same menus that were disabled in the x200 set.
There are also two regions not specified by the data sheet in the stock GBE, one is between offset 0x00A9-0x00E7 and the second is 0x0200-0x0583. I assume these are blobs related to Boot Agent.
Tom Hiller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 3:
Patch Set 3:
Patch Set 2: Code-Review+1
(1 comment)
Looks pretty good to me, did you test this by comparing what it generated to your actual GbE? If it was identical, we can probably merge this, or if it wasn't identical did you test on hw?
I tested it against the stock GBE and tested it on a X220. There are a few variations between this and the stock GBE, I used Intel defaults with the exception of the LEDs and disabling the same menus that were disabled in the x200 set.
There are also two regions not specified by the data sheet in the stock GBE, one is between offset 0x00A9-0x00E7 and the second is 0x0200-0x0583. I assume these are blobs related to Boot Agent.
To clarify, on physical hardware I tested internet conductivity, speed test was the same and appropriate device identification. I did not test PXE or Boot Agent to ensure they were fully disabled nor did I test Wake on LAN.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44510/3/util/bincfg/Makefile File util/bincfg/Makefile:
https://review.coreboot.org/c/coreboot/+/44510/3/util/bincfg/Makefile@22 PS3, Line 22: # Use this target to generate GbE for X200 I'd say these don't really belong in here but in chipset/mainboard code, but that's for a different commit.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 3:
one comment left to resolve before this can go in.
Hello build bot (Jenkins), Patrick Georgi, Damien Zammit, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44510
to look at the new patch set (#4).
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Intel GBE 82579LM bincfg set and spec
Using bincfg, generate Intel 82579LM GBE region firmware.
* Intel 82579LM is used in Lenovo models including x220 and x230. * PXE is disabled. * Intel 82579V variant could be generated with a few modifications to set. Noted in set file comments.
Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963 Signed-off-by: Tom Hiller thrilleratplay@gmail.com --- M util/bincfg/Makefile A util/bincfg/gbe-82579LM.set A util/bincfg/gbe-82579LM.spec 3 files changed, 442 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44510/4
Tom Hiller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 4:
Patch Set 3:
one comment left to resolve before this can go in.
Sorry, someone in the IRC chatroom mentioned that and I thought I pushed that fix.
Tom Hiller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 4:
(1 comment)
Sorry, someone in the IRC chatroom mentioned that and I thought I pushed that fix.
https://review.coreboot.org/c/coreboot/+/44510/3/util/bincfg/Makefile File util/bincfg/Makefile:
https://review.coreboot.org/c/coreboot/+/44510/3/util/bincfg/Makefile@22 PS3, Line 22: # Use this target to generate GbE for X200
I'd say these don't really belong in here but in chipset/mainboard code, but that's for a different […]
This has bee updated.
Tom Hiller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 4: Code-Review+2
Tom Hiller has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Removed Code-Review+2 by Tom Hiller thrilleratplay@gmail.com
Tom Hiller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 4:
Patch Set 2: Code-Review+1
(1 comment)
Looks pretty good to me, did you test this by comparing what it generated to your actual GbE? If it was identical, we can probably merge this, or if it wasn't identical did you test on hw?
I tested internet conductivity, speed test was the same and appropriate device identification. I did not test PXE or Boot Agent to ensure they were fully disabled nor did I test Wake on LAN. tlaurion of osresearch/heads also verified it is functional and is being included in the heads build.
Tom Hiller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 4:
(1 comment)
Updated Makefile comment.
https://review.coreboot.org/c/coreboot/+/44510/2/util/bincfg/Makefile File util/bincfg/Makefile:
https://review.coreboot.org/c/coreboot/+/44510/2/util/bincfg/Makefile@22 PS2, Line 22: # Use this target to generate GbE for X200
This should be X220/X230 instead of X200.
Done
Tom Hiller has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44510 )
Change subject: Intel GBE 82579LM bincfg set and spec ......................................................................
Intel GBE 82579LM bincfg set and spec
Using bincfg, generate Intel 82579LM GBE region firmware.
* Intel 82579LM is used in Lenovo models including x220 and x230. * PXE is disabled. * Intel 82579V variant could be generated with a few modifications to set. Noted in set file comments.
Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963 Signed-off-by: Tom Hiller thrilleratplay@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44510 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com --- M util/bincfg/Makefile A util/bincfg/gbe-82579LM.set A util/bincfg/gbe-82579LM.spec 3 files changed, 442 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Tom Hiller: Looks good to me, approved
diff --git a/util/bincfg/Makefile b/util/bincfg/Makefile index 1b3e936..f568e67 100644 --- a/util/bincfg/Makefile +++ b/util/bincfg/Makefile @@ -19,6 +19,13 @@ cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin rm -f gbe1.bin
+# Use this target to generate GbE for X220/x230 +gen-gbe-82579LM: + ./bincfg gbe-82579LM.spec gbe-82579LM.set gbe1.bin + # duplicate binary as per spec + cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin + rm -f gbe1.bin + # Use this target to generate IFD for X200 gen-ifd-x200: ./bincfg ifd-x200.spec ifd-x200.set flashregion_0_fd.bin diff --git a/util/bincfg/gbe-82579LM.set b/util/bincfg/gbe-82579LM.set new file mode 100644 index 0000000..01ae470 --- /dev/null +++ b/util/bincfg/gbe-82579LM.set @@ -0,0 +1,288 @@ +# SPDX-License-Identifier: GPL-3.0-or-later + +# +# Datasheets: +# +# https://cdrdv2.intel.com/v1/dl/getContent/613456 + +# The datasheet says that this spec covers the following pci ids: +# 8086:1502 - Intel 82579LM gigabit ethernet controller +# 8086:1503 - Intel 82579V gigabit ethernet controller + +# Naming convention +# * Word groups separated by a blank line +# * Word groups with known meaning given a prefix +# * prefix will be defined in comment before group +# * Variable names to be named using a prefix, descriptive name and bit offset +# within the word, separated by an underscore. +# * Example: "prefix_description_0" +# * Unidentified reserved word groups will be named reserved and LAN Word +# * EXCEPTION: Word 0x24, Word 0x25, Word 0x26 also include bit offset +# within the word +# Offset hex address, separated by an underscore. +# * Example: "reserved_x03" +# * Nonprefixed names will be named reserved and LAN Word Offset hex address, +# separated by an underscore. +# * Example: "imageversioninfo_x05" +# * Unspecified words are prefixed with "offset_" + +# GbE values for 82579LM +{ + # This example sets MAC address to 00:DE:AD:C0:FF:EE + # USE YOUR DEVICES MAC ADDRESS!! + # prefix: "mac_" + "mac_address_0" = 0x00, + "mac_address_1" = 0xDE, + "mac_address_2" = 0xAD, + "mac_address_3" = 0xC0, + "mac_address_4" = 0xFF, + "mac_address_5" = 0xEE, + + # Reserved (Word 0x3) + "reserved_x03" = 0x0800, + + # Reserved (Word 0x04) + "reserved_x04" = 0xffff, + + # Image Version Information (Word 0x05) + "imageversioninfo_x05" = 0x00D3, + + "reserved_x06" = 0xffff, + "reserved_x07" = 0xffff, + + # PBA Low and PBA High (Words 0x08 and 0x09) + # prefix: "pba_" + "pba_low_x08" = 0xffff, + "pba_high_x09" = 0xffff, + + # PCI Init Control Word (Word 0x0A) + # prefix: "pci_" + "pci_loaddeviceid_0" = 1, + "pci_loadsubsystemid_1" = 1, + "pci_reserved_2" = 0, + "pci_reserved_3" = 0x0, + "pci_pmenable_6" = 1, + "pci_auxpwr_7" = 1, + "pci_reserved_8" = 0x10, + + # ************* Configurable PCI IDs **************** + # TODO: make command line switch for these + # Subsystem ID (Word 0x0B) + "subsystemid_x0B" = 0, + # Subsystem Vendor ID (Word 0x0C) + "subsystemvendorid_x0C" = 0x8086, + # Device ID (Word 0x0D) + # TODO: 82579V uses "deviceid_x0D" = 0x1503, + "deviceid_x0D" = 0x1502, + # ************* END Configurable PCI IDs **************** + + # Words 0x0E and 0x0F Are Reserved + "reserved_x0E" = 0x0, + "reserved_x0F" = 0x0, + + # LAN Power Consumption (Word 0x10) + # prefix: "lanpwr_" + "lanpwr_d3pwr_0" = 0x2, + "lanpwr_reserved_5" = 0, + "lanpwr_d0pwr_8" = 0x7, + + # Word 0x12 and Word 0x11 Are Reserved + "reserved_x11" = 0x0000, + "reserved_x12" = 0x0000, + + # Shared Init Control Word (Word 0x13) + # prefix: "sicw_" + "sicw_dynamicclock_0" = 1, + "sicw_clkcnt_1" = 0, + "sicw_reserved_2" = 1, + "sicw_fullduplex_3" = 0, + "sicw_forcespeed_4" = 0, + "sicw_reserved_5" = 0, + "sicw_phydeviceype_6" = 0, + "sicw_reserved_8" = 1, + "sicw_phy_enpwrdown_9" = 0, + "sicw_reserved_10" = 1, + "sicw_macsecdisable_13" = 1, + "sicw_sign_14" = 0x2, + + # Extended Configuration Word 1 (Word 0x14) + # prefix: "ecw1_" + "ecw1_extcfgptr_0" = 0x0028, + "ecw1_oemload_12" = 1, + "ecw1_phyload_13" = 1, + "ecw1_reserved_14" = 0, + + # Extended Configuration Word 2 (Word 0x15) + # prefix: "ecw2_" + "ecw2_reserved_0" = 0x00, + "ecw2_extphylen_8" = 0x12, + + # Extended Configuration Word 3 (Word 0x16) + # prefix: "ecw3_" + "ecw3_extcfg1_0" = 0x00, + + # OEM Configuration Defaults (Word 0x17) + # prefix: "oem_" + "oem_reserved_0" = 0x000, + "oem_lpluenind0a_9" = 0, + "oem_lplueninnond0a_10" = 1, + "oem_gbedisinnond0a_11" = 1, + "oem_reserved_12" = 0, + "oem_gbedis_14" = 0, + "oem_reserved_15" = 0, + + # LED 0 - 2 Configuration Defaults (Word 0x18) + # prefix: "l02_" + # Lenovo default values + "l02_led0mode_0" = 0x4, + "l02_led0invert_3" = 0, + "l02_led0blink_4" = 0, + "l02_led1mode_5" = 0x3, + "l02_led1invert_8" = 0, + "l02_led1blink_9" = 1, + "l02_led2mode_10" = 0x2, + "l02_led2invert_13" = 1, + "l02_led2blink_14" = 0, + "l02_blinkrate_15" = 0, + + # Intel default Values + #"l02_led0mode_0" = 0x4, + #"l02_led0invert_3" = 0, + #"l02_led0blink_4" = 1, + #"l02_led1mode_5" = 0x7, + #"l02_led1invert_8" = 0, + #"l02_led1blink_9" = 0, + #"l02_led2mode_10" = 0x6, + #"l02_led2invert_13" = 0, + #"l02_led2blink_14" = 0, + #"l02_blinkrate_15" = 0, + + + # Reserved (Word 0x19) + # NOTE: bit 6 must be 1 for validation. See datasheet. + "reserved_x19" = 0x2B40, + + # Reserved (Word 0x1A) + # Advanced Power Management Wake Up Enable + # prefix: "amp_" + "amp_enable_0" = 1, + "amp_reserved_1" = 0x0421, + + # Reserved (Word 0x1B) + "reserved_x1B" = 0x0113, + + # Reserved (Word 0x1C) + "reserved_x1C" = 0x1502, + + # Reserved (Word 0x1D) + "reserved_x1D" = 0xBAAD, + + # Reserved (Word 0x1E) + "reserved_x1E" = 0x1502, + + # Reserved (Word 0x1F) + "reserved_x1F" = 0x1503, + + # Reserved (Word 0x20) + "reserved_x20" = 0xBAAD, + + # Reserved (Word 0x21) + "reserved_x21" = 0xBAAD, + + # Reserved (Word 0x22) + "reserved_x22" = 0xBAAD, + + # Reserved (Word 0x23) + "reserved_x23" = 0x1502, + + # Reserved (Word 0x24) + "reserved_x24_0" = 0x0000, + "reserved_x24_14" = 0, + "reserved_x24_15" = 1, + + # Reserved (Word 0x25) + "reserved_x25_0" = 0x0000, + "reserved_x25_4" = 1, + "reserved_x25_5" = 0, + "reserved_x25_7" = 1, + "reserved_x25_8" = 0x00, + "reserved_x25_15" = 1, + + # Reserved (Word 0x26) + "reserved_x26_0" = 0x00, + "reserved_x26_9" = 1, + "reserved_x26_10" = 1, + "reserved_x26_11" = 1, + "reserved_x26_12" = 0, + "reserved_x26_14" = 1, + "reserved_x26_15" = 0, + + # Reserved (Word 0x27) + "reserved_x27" = 0x80, + + # Offsets 0x28-0x2F + "offset_x28" = 0x0000, + "offset_x29" = 0x0000, + "offset_x2A" = 0x0000, + "offset_x2B" = 0x0000, + "offset_x2C" = 0x0000, + "offset_x2D" = 0x0000, + "offset_x2E" = 0x0000, + "offset_x2F" = 0x0000, + + # Boot Agent Main Setup Options (Word 0x30) + # Hardcoded PXE setup (disabled) + # prefix: "pxe30_" + "pxe30_protocolsel_0" = 0, + "pxe30_reserved_2" = 0, + "pxe30_defbootsel_3" = 0x3, + "pxe30_reserved_5" = 0, + "pxe30_prompttime_6" = 0x3, + "pxe30_dispsetup_8" = 0, + "pxe30_reserved_9" = 0, + "pxe30_forcespeed_10" = 0, + "pxe30_forcefullduplex_12" = 0, + "pxe30_reserved_13" = 0, + "pxe30_reserved_14" = 0, + + # Boot Agent Configuration Customization Options (Word 0x31) + # prefix: "pxe31_" + "pxe31_disablemenu_0" = 1, + "pxe31_disabletitle_1" = 1, + "pxe31_disableprotsel_2" = 0, + "pxe31_disbootorder_3" = 0, + "pxe31_dislegacywak_4" = 0, + "pxe31_disableflasicwpro_5" = 0, + "pxe31_reserved_6" = 0, + "pxe31_ibootagentmode_8" = 0, + "pxe31_contretrydis_11" = 0, + "pxe31_reserved_12" = 0, + "pxe31_signature_14" = 10, + + # Boot Agent Configuration Customization Options (Word 0x32) + # prefix: "pxe32_" + "pxe32_buildnum_0" = 0x28, + "pxe32_minorversion_8" = 0x2, + "pxe32_majorversion_12" = 0x1, + + # IBA Capabilities (Word 0x33) + # prefix: "pxe33_" + "pxe33_basecodepresent_0" = 1, + "pxe33_undipresent_1" = 1, + "pxe33_reserved_2" = 1, + "pxe33_efiundipresent_3" = 0, + "pxe33_iscsi_4" = 0, + "pxe33_reserved_5" = 0, + "pxe33_signature_14" = 10, + + "pxe_padding"[11] = 0xffff, + + # Checksum is generated by bincfg + # "checksum_gbe" = xxx, + + # G3 -> S5 PHY Configuration + "g3_s5_phy_conf"[0x16] = 0, + + # Padding 0xf80 bytes + "padding"[0xf6a] = 0xff +} diff --git a/util/bincfg/gbe-82579LM.spec b/util/bincfg/gbe-82579LM.spec new file mode 100644 index 0000000..0367aff --- /dev/null +++ b/util/bincfg/gbe-82579LM.spec @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: GPL-3.0-or-later +# +# Datasheets: +# +# https://cdrdv2.intel.com/v1/dl/getContent/613456 + +# The datasheet says that this spec covers the following pci ids: +# 8086:1502 - Intel 82579LM gigabit ethernet controller +# 8086:1503 - Intel 82579V gigabit ethernet controller + +# GbE SPEC for 82579LM/82579V +{ + "mac_address_"[6] : 8, + "reserved_x03" : 16, + "reserved_x04" : 16, + "imageversioninfo_x05" : 16, + "reserved_x06" : 16, + "reserved_x07" : 16, + "pba_low_x08" : 16, + "pba_high_x09" : 16, + "pci_loaddeviceid_0" : 1, + "pci_loadsubsystemid_1" : 1, + "pci_reserved_2" : 1, + "pci_reserved_3" : 3, + "pci_pmenable_6" : 1, + "pci_auxpwr_7" : 1, + "pci_reserved_8" : 8, + "subsystemid_x0B" : 16, + "subsystemvendorid_x0C" : 16, + "deviceid_x0D" : 16, + "reserved_x0E" : 16, + "reserved_x0F" : 16, + "lanpwr_d3pwr_0" : 5, + "lanpwr_reserved_5" : 3, + "lanpwr_d0pwr_8" : 8, + "reserved_x11" : 16, + "reserved_x12" : 16, + "sicw_dynamicclock_0" : 1, + "sicw_clkcnt_1" : 1, + "sicw_reserved_2" : 1, + "sicw_fullduplex_3" : 1, + "sicw_forcespeed_4" : 1, + "sicw_reserved_5" : 1, + "sicw_phydeviceype_6" : 2, + "sicw_reserved_8" : 1, + "sicw_phy_enpwrdown_9" : 1, + "sicw_reserved_10" : 3, + "sicw_macsecdisable_13" : 1, + "sicw_sign_14" : 2, + "ecw1_extcfgptr_0" : 12, + "ecw1_oemload_12" : 1, + "ecw1_phyload_13" : 1, + "ecw1_reserved_14" : 2, + "ecw2_reserved_0" : 8, + "ecw2_extphylen_8" : 8, + "ecw3_extcfg1_0" : 16, + "oem_reserved_0" : 9, + "oem_lpluenind0a_9" : 1, + "oem_lplueninnond0a_10" : 1, + "oem_gbedisinnond0a_11" : 1, + "oem_reserved_12" : 2, + "oem_gbedis_14" : 1, + "oem_reserved_15" : 1, + "l02_led0mode_0" : 3, + "l02_led0invert_3" : 1, + "l02_led0blink_4" : 1, + "l02_led1mode_5" : 3, + "l02_led1invert_8" : 1, + "l02_led1blink_9" : 1, + "l02_led2mode_10" : 3, + "l02_led2invert_13" : 1, + "l02_led2blink_14" : 1, + "l02_blinkrate_15" : 1, + "reserved_x19" : 16, + "amp_enable_0" : 1, + "amp_reserved_1" : 15, + "reserved_x1B" : 16, + "reserved_x1C" : 16, + "reserved_x1D" : 16, + "reserved_x1E" : 16, + "reserved_x1F" : 16, + "reserved_x20" : 16, + "reserved_x21" : 16, + "reserved_x22" : 16, + "reserved_x23" : 16, + "reserved_x24_0" : 14, + "reserved_x24_14" : 1, + "reserved_x24_15" : 1, + "reserved_x25_0" : 4, + "reserved_x25_4" : 1, + "reserved_x25_5" : 2, + "reserved_x25_7" : 1, + "reserved_x25_8" : 7, + "reserved_x25_15" : 1, + "reserved_x26_0" : 9, + "reserved_x26_9" : 1, + "reserved_x26_10" : 1, + "reserved_x26_11" : 1, + "reserved_x26_12" : 2, + "reserved_x26_14" : 1, + "reserved_x26_15" : 1, + "reserved_x27" : 16, + "offset_x28" : 16, + "offset_x29" : 16, + "offset_x2A" : 16, + "offset_x2B" : 16, + "offset_x2C" : 16, + "offset_x2D" : 16, + "offset_x2E" : 16, + "offset_x2F" : 16, + "pxe30_protocolsel_0" : 2, + "pxe30_reserved_2" : 1, + "pxe30_defbootsel_3" : 2, + "pxe30_reserved_5" : 1, + "pxe30_prompttime_6" : 2, + "pxe30_dispsetup_8" : 1, + "pxe30_reserved_9" : 1, + "pxe30_forcespeed_10" : 2, + "pxe30_forcefullduplex_12" : 1, + "pxe30_reserved_13" : 1, + "pxe30_reserved_14" : 2, + "pxe31_disablemenu_0" : 1, + "pxe31_disabletitle_1" : 1, + "pxe31_disableprotsel_2" : 1, + "pxe31_disbootorder_3" : 1, + "pxe31_dislegacywak_4" : 1, + "pxe31_disableflasicwpro_5" : 1, + "pxe31_reserved_6" : 2, + "pxe31_ibootagentmode_8" : 3, + "pxe31_contretrydis_11" : 1, + "pxe31_reserved_12" : 2, + "pxe31_signature_14" : 2, + "pxe32_buildnum_0" : 8, + "pxe32_minorversion_8" : 4, + "pxe32_majorversion_12" : 4, + "pxe33_basecodepresent_0" : 1, + "pxe33_undipresent_1" : 1, + "pxe33_reserved_2" : 1, + "pxe33_efiundipresent_3" : 1, + "pxe33_iscsi_4" : 1, + "pxe33_reserved_5" : 9, + "pxe33_signature_14" : 2, + "pxe_padding"[11] : 16, + "checksum_gbe" : 16, + "g3_s5_phy_conf"[0x16] : 8, + "padding"[0xf6a] : 8 +}
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Damien Zammit (Code Review) -
Patrick Georgi (Code Review)
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Tom Hiller (Code Review)