New patch to review for coreboot: During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width.

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13807

-gerrit

commit 9da1177c09d6748817964fad31d73b7658e9138f
Author: Timothy Pearson 
Date:   Thu Feb 25 23:20:14 2016 -0600

During DRAM initialization on certain ASpeed devices, an incorrect
    bit (bit 10) was checked in the "SDRAM Bus Width Status" register
    to determine DRAM width.

Query bit 6 instead in accordance with the Aspeed AST2050 datasheet
    v1.05.

Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26
    Signed-off-by: Timothy Pearson 
---
 src/drivers/aspeed/common/ast_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c
index 071e49c..264ef9d 100644
--- a/src/drivers/aspeed/common/ast_main.c
+++ b/src/drivers/aspeed/common/ast_main.c
@@ -232,7 +232,7 @@ static int ast_get_dram_info(struct drm_device *dev)

data = ast_read32(ast, 0x10004);

-	if (data & 0x400)
+	if (data & 0x40)
    	ast->dram_bus_width = 16;
    else
    	ast->dram_bus_width = 32;