[M] Change in coreboot[main]: intel/alderlake: Add helper functions for Power Management

[Sean Rhodes (Code Review)]

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eric Lai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Nico Huber, Paul Menzel, Sean Rhodes, Subrata Banik.

Hello Angel Pons, Dinesh Gehlot, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/81638?usp=email

to look at the new patch set (#18).

Change subject: intel/alderlake: Add helper functions for Power Management
......................................................................

intel/alderlake: Add helper functions for Power Management

Clock Power Management, ASPM and L1 Substates have been
configured the same way since SkyLake. The main control to
enable or disable is Kconfig, and then the level can be overridden
in devicetree.

Despite the UPDs remaining the same since SkyLake, this is not the
case for AlderLake, RaptorLake and MeteorLake.

Taking `starlabs/starbook` as an example, at the time of this
commit it has PCIEXP_CLK_PM, PCIEXP_ASPM and PCIEXP_L1_SUB_STATE
enabled.

On CometLake, this results in the correct configuration, verified
with the lspci command:
```
    LnkCap:	Port #0, Speed 5GT/s, Width x1, ASPM L1, Exit Latency L1 <8us
    	ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
    LnkCtl:	ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
    	ExtSynch- ClockPM+ AutWidDis- BWInt- AutBWInt-
```
On RaptorLake:

```
    LnkCap:	Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
    	ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
    LnkCtl:	ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
```

Clock Power Management, ASPM and L1 Substates are also not configured
for CPU root ports.

Add helper functions to configure these correctly based on Kconfig, but
retain the capability to override the specific levels from devicetree.

Change-Id: I9db18859f9a04ad4b7c0c3f7992b09e0f9484a81
Signed-off-by: Sean Rhodes 
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 111 insertions(+), 39 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81638/18