Change in coreboot[master]: soc/sifive: Drop unneeded empty lines - coreboot-gerrit

19 Aug 2020

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44602 )
Change subject: soc/sifive: Drop unneeded empty lines
......................................................................
soc/sifive: Drop unneeded empty lines
Change-Id: I20008c71d5b573d72a09068626523e10faa2d632
Signed-off-by: Elyes HAOUAS ehaouas@noos.fr
---
M src/soc/sifive/fu540/clock.c
M src/soc/sifive/fu540/ddrregs.h
M src/soc/sifive/fu540/spi.c
M src/soc/sifive/fu540/spi_internal.h
M src/soc/sifive/fu540/ux00ddr.h
5 files changed, 0 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44602/1

diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c
index 9b21532..977f938 100644
--- a/src/soc/sifive/fu540/clock.c
+++ b/src/soc/sifive/fu540/clock.c
@@ -177,7 +177,6 @@
    write32(&prci->gemgxlpllcfg1, cfg1);
 }
-
 #define FU540_UART_DEVICES 2
 #define FU540_UART_REG_DIV 0x18
 #define FU540_UART_DIV_VAL 4
@@ -185,7 +184,6 @@
 #define FU540_SPI_DIV 0x00
 #define FU540_SPI_DIV_VAL 4
-
 static void update_peripheral_clock_dividers(void)
 {
    write32((uint32_t *)(FU540_QSPI0 + FU540_SPI_DIV), FU540_SPI_DIV_VAL);
diff --git a/src/soc/sifive/fu540/ddrregs.h b/src/soc/sifive/fu540/ddrregs.h
index 78b6dce..8786f68 100644
--- a/src/soc/sifive/fu540/ddrregs.h
+++ b/src/soc/sifive/fu540/ddrregs.h
@@ -140,7 +140,6 @@
 DENALI_PHY_1200_DATA, DENALI_PHY_1201_DATA, DENALI_PHY_1202_DATA, DENALI_PHY_1203_DATA, DENALI_PHY_1204_DATA, DENALI_PHY_1205_DATA, DENALI_PHY_1206_DATA, DENALI_PHY_1207_DATA, DENALI_PHY_1208_DATA, DENALI_PHY_1209_DATA,
 DENALI_PHY_1210_DATA, DENALI_PHY_1211_DATA, DENALI_PHY_1212_DATA, DENALI_PHY_1213_DATA, DENALI_PHY_1214_DATA};
-
 uint32_t DENALI_CTL_DATA[265] = {
 DENALI_CTL_00_DATA, DENALI_CTL_01_DATA, DENALI_CTL_02_DATA, DENALI_CTL_03_DATA, DENALI_CTL_04_DATA, DENALI_CTL_05_DATA, DENALI_CTL_06_DATA, DENALI_CTL_07_DATA, DENALI_CTL_08_DATA, DENALI_CTL_09_DATA,
 DENALI_CTL_10_DATA, DENALI_CTL_11_DATA, DENALI_CTL_12_DATA, DENALI_CTL_13_DATA, DENALI_CTL_14_DATA, DENALI_CTL_15_DATA, DENALI_CTL_16_DATA, DENALI_CTL_17_DATA, DENALI_CTL_18_DATA, DENALI_CTL_19_DATA,
diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c
index d877452..87c59a4 100644
--- a/src/soc/sifive/fu540/spi.c
+++ b/src/soc/sifive/fu540/spi.c
@@ -13,7 +13,6 @@
    (struct spi_ctrl *)FU540_QSPI2
 };
-
 /**
  * Wait until SPI is ready for transmission and transmit byte.
  */
@@ -35,7 +34,6 @@
 #endif
 }
-
 /**
  * Wait until SPI receive queue has data and read byte.
  */
diff --git a/src/soc/sifive/fu540/spi_internal.h b/src/soc/sifive/fu540/spi_internal.h
index bdddf4f..96124c1 100644
--- a/src/soc/sifive/fu540/spi_internal.h
+++ b/src/soc/sifive/fu540/spi_internal.h
@@ -22,7 +22,6 @@
 } spi_reg_sckmode;
 _ASSERT_SIZEOF(spi_reg_sckmode, 4);
-
 typedef union {
    struct {
    	uint32_t mode : 2;
@@ -32,7 +31,6 @@
 } spi_reg_csmode;
 _ASSERT_SIZEOF(spi_reg_csmode, 4);
-
 typedef union {
    struct {
    	uint32_t cssck : 8;
@@ -44,7 +42,6 @@
 } spi_reg_delay0;
 _ASSERT_SIZEOF(spi_reg_delay0, 4);
-
 typedef union {
    struct {
    	uint32_t intercs : 8;
@@ -56,7 +53,6 @@
 } spi_reg_delay1;
 _ASSERT_SIZEOF(spi_reg_delay1, 4);
-
 typedef union {
    struct {
    	uint32_t proto : 2;
@@ -70,7 +66,6 @@
 } spi_reg_fmt;
 _ASSERT_SIZEOF(spi_reg_fmt, 4);
-
 typedef union {
    struct {
    	uint32_t data : 8;
@@ -81,7 +76,6 @@
 } spi_reg_txdata;
 _ASSERT_SIZEOF(spi_reg_txdata, 4);
-
 typedef union {
    struct {
    	uint32_t data : 8;
@@ -92,7 +86,6 @@
 } spi_reg_rxdata;
 _ASSERT_SIZEOF(spi_reg_rxdata, 4);
-
 typedef union {
    struct {
    	uint32_t txmark : 3;
@@ -102,7 +95,6 @@
 } spi_reg_txmark;
 _ASSERT_SIZEOF(spi_reg_txmark, 4);
-
 typedef union {
    struct {
    	uint32_t rxmark : 3;
@@ -112,7 +104,6 @@
 } spi_reg_rxmark;
 _ASSERT_SIZEOF(spi_reg_rxmark, 4);
-
 typedef union {
    struct {
    	uint32_t en : 1;
@@ -122,7 +113,6 @@
 } spi_reg_fctrl;
 _ASSERT_SIZEOF(spi_reg_fctrl, 4);
-
 typedef union {
    struct {
    	uint32_t cmd_en : 1;
@@ -139,7 +129,6 @@
 } spi_reg_ffmt;
 _ASSERT_SIZEOF(spi_reg_ffmt, 4);
-
 typedef union {
    struct {
    	uint32_t txwm : 1;
@@ -154,7 +143,6 @@
#undef _ASSERT_SIZEOF
-
 /**
  * SPI control register memory map.
  *
diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h
index 565103b..14a628d 100644
--- a/src/soc/sifive/fu540/ux00ddr.h
+++ b/src/soc/sifive/fu540/ux00ddr.h
@@ -47,7 +47,6 @@
   }
 }
-
 static inline void ux00ddr_writeregmap(size_t ahbregaddr, const uint32_t *ctlsettings, const uint32_t *physettings) {
   volatile uint32_t *ddrctlreg = (volatile uint32_t *) ahbregaddr;
   volatile uint32_t *ddrphyreg = ((volatile uint32_t *) ahbregaddr) + (0x2000 / sizeof(uint32_t));
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I20008c71d5b573d72a09068626523e10faa2d632
Gerrit-Change-Number: 44602
Gerrit-PatchSet: 1
Gerrit-Owner: HAOUAS Elyes ehaouas@noos.fr
Gerrit-MessageType: newchange



    