Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83948?usp=email )
Change subject: soc/intel/common/block/cpu: Fix ways count computation regression ......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83948/comment/396eabff_c2d26a68?usp... : PS11, Line 32: TEST=Verified on PTL Intel reference platform
I performed the following experiment: […]
Sorry, I though the question was for https://review.coreboot.org/c/coreboot/+/83946/10.
To verify this particular issue, I use a configuration with `CONFIG_DCACHE_RAM_SIZE > Effective way size` and then there a couple of options to observe the bug/fix: 1. Use a debugger, run a step by step and look at the registers 2. Dump some register using the post_code() macro in the algorithm
I used #2 as it was faster for me. I created the following temporary macro for this purpose.
``` modified src/include/cpu/x86/post_code.h @@ -9,7 +9,25 @@ #define post_code(value) \ movb $value, %al; \ outb %al, $CONFIG_POST_IO_PORT - +#define post_code_safe(value, backup) \ + mov %eax, backup; \ + movb $value, %al; \ + outb %al, $CONFIG_POST_IO_PORT; \ + mov backup, %eax; +#define dump_register(reg, backup) \ + mov %eax, backup; \ + movb $0xa, %al; \ + outb %al, $CONFIG_POST_IO_PORT; \ + mov backup, %eax; \ + mov reg, %eax; \ + outb %al, $CONFIG_POST_IO_PORT; \ + shrl $8, %eax; \ + outb %al, $CONFIG_POST_IO_PORT; \ + shrl $8, %eax; \ + outb %al, $CONFIG_POST_IO_PORT; \ + shrl $8, %eax; \ + outb %al, $CONFIG_POST_IO_PORT; \ + mov backup, %eax; #else #define post_code(value) ```