Change in coreboot[master]: soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47141 )
Change subject: soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix ......................................................................
soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix
This change adds elog.c to smm-y for Tiger lake and Jasper Lake platforms to enable the logging of wake sources in eventlog for S0ix.
BUG=b:172272078,b:169731044 BRANCH=volteer TEST=Verified on volteer that wake sources are correctly logged for S0ix: 8 | 2020-11-02 13:54:27 | S0ix Enter 9 | 2020-11-02 13:54:33 | S0ix Exit 10 | 2020-11-02 13:54:33 | Wake Source | RTC Alarm | 0 11 | 2020-11-02 13:54:49 | S0ix Enter 12 | 2020-11-02 13:54:54 | S0ix Exit 13 | 2020-11-02 13:54:54 | Wake Source | Power Button | 0 14 | 2020-11-02 13:55:04 | S0ix Enter 15 | 2020-11-02 13:55:10 | S0ix Exit 16 | 2020-11-02 13:55:10 | Wake Source | GPE # | 112
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ie1c40dfba6c82ca45a21d35c5a2725e4d30855d6 --- M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/tigerlake/Makefile.inc 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/47141/1
diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 1cba218..209d8a2 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -51,6 +51,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += elog.c
verstage-y += gpio.c
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..a25d0a4 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -50,6 +50,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += elog.c
verstage-y += gpio.c
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47141 )
Change subject: soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix ......................................................................
Patch Set 1: Code-Review+2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47141 )
Change subject: soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix ......................................................................
Patch Set 1: Code-Review+2
Works fine in JSL/Dedede as well.
8 | 2020-11-02 15:11:59 | S0ix Enter 9 | 2020-11-02 15:12:03 | S0ix Exit 10 | 2020-11-02 15:12:03 | Wake Source | RTC Alarm | 0 11 | 2020-11-02 15:12:27 | S0ix Enter 12 | 2020-11-02 15:12:32 | S0ix Exit 13 | 2020-11-02 15:12:32 | Wake Source | GPE # | 112 14 | 2020-11-02 15:12:32 | EC Event | Key Pressed 15 | 2020-11-02 15:13:24 | S0ix Enter 16 | 2020-11-02 15:13:40 | S0ix Exit 17 | 2020-11-02 15:13:40 | Wake Source | GPE # | 3
Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47141 )
Change subject: soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix ......................................................................
soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix
This change adds elog.c to smm-y for Tiger lake and Jasper Lake platforms to enable the logging of wake sources in eventlog for S0ix.
BUG=b:172272078,b:169731044 BRANCH=volteer TEST=Verified on volteer that wake sources are correctly logged for S0ix: 8 | 2020-11-02 13:54:27 | S0ix Enter 9 | 2020-11-02 13:54:33 | S0ix Exit 10 | 2020-11-02 13:54:33 | Wake Source | RTC Alarm | 0 11 | 2020-11-02 13:54:49 | S0ix Enter 12 | 2020-11-02 13:54:54 | S0ix Exit 13 | 2020-11-02 13:54:54 | Wake Source | Power Button | 0 14 | 2020-11-02 13:55:04 | S0ix Enter 15 | 2020-11-02 13:55:10 | S0ix Exit 16 | 2020-11-02 13:55:10 | Wake Source | GPE # | 112
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ie1c40dfba6c82ca45a21d35c5a2725e4d30855d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47141 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/tigerlake/Makefile.inc 2 files changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 1cba218..209d8a2 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -51,6 +51,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += elog.c
verstage-y += gpio.c
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..a25d0a4 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -50,6 +50,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += elog.c
verstage-y += gpio.c
-
Furquan Shaikh (Code Review) -
Karthik Ramasubramanian (Code Review)
-
Tim Wawrzynczak (Code Review)