[L] Change in coreboot[main]: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support

[Angel Pons (Code Review)]

Attention is currently required from: Alicja Michalska, David Milosevic.

Angel Pons has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email )

Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
......................................................................

Patch Set 2:

(5 comments)

File src/mainboard/hardkernel/odroid-h4/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/83979/comment/6cf2e774_8e5fc087?usp... :
PS2, Line 84: 		#		.clk_src = 2,
> On most ADL-N systems, M.2 NVME is connected to Clock Source 0. […]

Nice, schematics are also available from the Odroid wiki: https://wiki.odroid.com/_media/odroid-h4/hardware/adln-h4_sch_2024-0306.pdf

https://review.coreboot.org/c/coreboot/+/83979/comment/d8cb4db5_09ea5ffb?usp... :
PS2, Line 82: #device ref pcie_rp3 on
            : 		#	register "pch_pcie_rp[PCH_RP(3)]" = "{
            : 		#		.clk_src = 2,
            : 		#		.clk_req = 2,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#	smbios_slot_desc	"SlotTypeM2Socket3" "SlotLengthOther"
            : 		#				"M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X"
            : 		#end
            : 		#device ref pcie_rp7 on	# LAN1
            : 		#	register "pch_pcie_rp[PCH_RP(7)]" = "{
            : 		#		.clk_src = 3,
            : 		#		.clk_req = 3,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#end
            : 		#device ref pcie_rp9 on	# LAN2
            : 		#	register "pch_pcie_rp[PCH_RP(9)]" = "{
            : 		#		.clk_src = 0,
            : 		#		.clk_req = 0,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#end
            : 		#device ref pcie_rp10 on
            : 		#	register "pch_pcie_rp[PCH_RP(10)]" = "{
            : 		#		.clk_src = 1,
            : 		#		.clk_req = 1,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#	smbios_slot_desc	"SlotTypeM2Socket1_SD" "SlotLengthOther"
            : 		#				"M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X"
            : 		#end
I've left it commented out so that the differences are easier to see, but you should obviously uncomment it:

```suggestion
    	#device ref pcie_rp3 on # LAN1
    	#	register "pch_pcie_rp[PCH_RP(3)]" = "{
    	#		.clk_src = 1,
    	#		.clk_req = 1,
    	#		.flags = PCIE_RP_CLK_REQ_DETECT,
    	#	}"
    	#end
    	#device ref pcie_rp4 on	# LAN2
    	#	register "pch_pcie_rp[PCH_RP(4)]" = "{
    	#		.clk_src = 2,
    	#		.clk_req = 2,
    	#		.flags = PCIE_RP_CLK_REQ_DETECT,
    	#	}"
    	#end
    	#device ref pcie_rp7 on	# ASM1064B SATA
    	#	register "pch_pcie_rp[PCH_RP(7)]" = "{
    	#		.clk_src = 3,
    	#		.flags = PCIE_RP_CLK_REQ_UNUSED,
    	#	}"
    	#end
    	#device ref pcie_rp9 on # M.2 SSD
    	#	register "pch_pcie_rp[PCH_RP(9)]" = "{
    	#		.clk_src = 0,
    	#		.clk_req = 0,
    	#		.flags = PCIE_RP_CLK_REQ_DETECT,
    	#	}"
    	#	smbios_slot_desc	"SlotTypeM2Socket3" "SlotLengthOther"
    	#				"M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X"
    	#end
```

https://review.coreboot.org/c/coreboot/+/83979/comment/e2441410_b81f25ce?usp... :
PS2, Line 148: 				device pnp 2e.a on end # CIR
CIR seems unused as well

https://review.coreboot.org/c/coreboot/+/83979/comment/3187d3e2_c66af2b9?usp... :
PS2, Line 151: 	device ref uart0 on
             : 			register "serial_io_uart_mode" = "{
             : 				[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
             : 			}"
             : 		end
I can't see this being used in the schematics, the UART on the 2x12 header comes from the IT8613E Super I/O

https://review.coreboot.org/c/coreboot/+/83979/comment/273d6ed7_a7c39893?usp... :
PS2, Line 156: 	device ref gspi0 on
             : 			register "serial_io_gspi_mode" = "{
             : 				[PchSerialIoIndexGSPI0] = PchSerialIoPci,
             : 			}"
             : 		end
GSPI0 pins are disconnected in the schematic, this can be disabled.