Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46761 )
Change subject: soc/intel/broadwell/pch/acpi: Add PCIe register offsets ......................................................................
soc/intel/broadwell/pch/acpi: Add PCIe register offsets
These are present in common southbridge ACPI code, and also exist on Broadwell. Thus, add the definitions to align with common ACPI code.
Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/pch/acpi/pcie_port.asl 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46761/1
diff --git a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl index d48ecd0..988c817 100644 --- a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl +++ b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl @@ -8,4 +8,10 @@ Offset (0x4c), // Link Capabilities , 24, RPPN, 8, // Root Port Number + Offset (0x5A), + , 3, + PDC, 1, + Offset (0xDF), + , 6, + HPCS, 1, }
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46761 )
Change subject: soc/intel/broadwell/pch/acpi: Add PCIe register offsets ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46761/10/src/soc/intel/broadwell/pc... File src/soc/intel/broadwell/pch/acpi/pcie_port.asl:
https://review.coreboot.org/c/coreboot/+/46761/10/src/soc/intel/broadwell/pc... PS10, Line 11: 5A nit, 0x5a?
https://review.coreboot.org/c/coreboot/+/46761/10/src/soc/intel/broadwell/pc... PS10, Line 14: DF nit, 0xdf
Actually, `Offset (0xdc), , 30,` would be much nicer.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46761 )
Change subject: soc/intel/broadwell/pch/acpi: Add PCIe register offsets ......................................................................
Patch Set 10: Code-Review+2
(1 comment)
Turned out this change wasn't meant for review but to get a follow-up checked by binary comparison. It would be much easier when that's mentioned in the commit message.
https://review.coreboot.org/c/coreboot/+/46761/10/src/soc/intel/broadwell/pc... File src/soc/intel/broadwell/pch/acpi/pcie_port.asl:
https://review.coreboot.org/c/coreboot/+/46761/10/src/soc/intel/broadwell/pc... PS10, Line 14: DF
nit, 0xdf […]
Hrmmm, looks like this change was never meant for review.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46761 )
Change subject: soc/intel/broadwell/pch/acpi: Add PCIe register offsets ......................................................................
Patch Set 10: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46761/10//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46761/10//COMMIT_MSG@10 PS10, Line 10: Broadwell. Thus, add the definitions to align with common ACPI code. not documented, but I presume so as well
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46761 )
Change subject: soc/intel/broadwell/pch/acpi: Add PCIe register offsets ......................................................................
soc/intel/broadwell/pch/acpi: Add PCIe register offsets
These are present in common southbridge ACPI code, and also exist on Broadwell. Thus, add the definitions to align with common ACPI code.
Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46761 Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/broadwell/pch/acpi/pcie_port.asl 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl index d48ecd0..988c817 100644 --- a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl +++ b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl @@ -8,4 +8,10 @@ Offset (0x4c), // Link Capabilities , 24, RPPN, 8, // Root Port Number + Offset (0x5A), + , 3, + PDC, 1, + Offset (0xDF), + , 6, + HPCS, 1, }
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Angel Pons (Code Review) -
Nico Huber (Code Review)
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Tim Wawrzynczak (Code Review)