[M] Change in coreboot[main]: drivers/intel/fsp2_0: Simplify FSP global reset definition

[Jérémy Compostella (Code Review)]

Attention is currently required from: Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Lean Sheng Tan, Nick Vaccaro, Paul Menzel, Pranava Y N, Rishika Raj, Ronak Kanabar, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh.

Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84356?usp=email )

Change subject: drivers/intel/fsp2_0: Simplify FSP global reset definition
......................................................................

Patch Set 3:

(7 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/84356/comment/81153ea4_776abc92?usp... :
PS2, Line 9: which
> whose?

Done

https://review.coreboot.org/c/coreboot/+/84356/comment/269d2241_b570e647?usp... :
PS2, Line 13: take
> takes

Done

https://review.coreboot.org/c/coreboot/+/84356/comment/4f59700b_63f219bb?usp... :
PS2, Line 17: TEST=Verified with fatcat mainboard on pantherlake reference board
> Before it did not boot or build?

Done

File src/drivers/intel/fsp2_0/Kconfig:

https://review.coreboot.org/c/coreboot/+/84356/comment/f5d420c8_be638668?usp... :
PS2, Line 378: 0x4000000000000003
> can you please point me to the FSP spec that defines 64-bit FSP return value. […]

FSP 2.4 OEM Status Code https://cdrdv2.intel.com/v1/dl/getContent/736809?explicitVersion=true.

But technically speaking this return status always has been an EFI_STATUS which per definition varies with the architecture but since FSP < 2.3 was limited to 32-bit it was not an issue.

File src/include/efi/efi_datatype.h:

https://review.coreboot.org/c/coreboot/+/84356/comment/825c0df9_3649a31b?usp... :
PS2, Line 16: #if CONFIG(PLATFORM_USES_FSP1_1) || CONFIG(PLATFORM_USES_FSP2_X86_32)
> can u please submit a separate CL to add FSP1. […]

Done

File src/soc/intel/meteorlake/chip.c:

https://review.coreboot.org/c/coreboot/+/84356/comment/903f4703_4cbcbf82?usp... :
PS2, Line 276: 	fsp_die_with_post_code(reset_status, POSTCODE_HW_INIT_FAILURE,
             : 		 "Failed to handle the FSP reset request");
> please submit a separate CL for this as well

Done

File src/soc/intel/pantherlake/chip.c:

https://review.coreboot.org/c/coreboot/+/84356/comment/376179bc_7e8a02f3?usp... :
PS2, Line 274: 	fsp_die_with_post_code(reset_status, POSTCODE_HW_INIT_FAILURE,
             : 		 "Failed to handle the FSP reset request");
> same as previous file

I cannot, if I split, I hit the following error:
```
src/soc/intel/pantherlake/chip.c:275:74: note: format string is defined here
  275 |                  "Failed to handle the FSP reset request with error 0x%08x\n", reset_status);
      |                                                                       ~~~^
      |                                                                          |
      |                                                                          unsigned int
      |                                                                       %08llx
cc1: all warnings being treated as errors
```