Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42038 )
Change subject: mb/pcengines/apu2: Change GPIO configuration functions ......................................................................
mb/pcengines/apu2: Change GPIO configuration functions
The definitions of GPIO_xx equal IOMUX_GPIO_xx shifted by two.
Change-Id: I0ee821c71c88bf535122a9526862a9d1e68bd755 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/gpio_ftns.h M src/mainboard/pcengines/apu2/romstage.c 3 files changed, 38 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/42038/1
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index 1969a88..c249c2d 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -7,8 +7,10 @@ #include <FchPlatform.h> #include "gpio_ftns.h"
-static u32 gpio_read_wrapper(u32 gpio) +static u32 gpio_read_wrapper(u32 iomux_gpio) { + u32 gpio = iomux_gpio << 2; + if (gpio < 0x100) return gpio0_read32(gpio & 0xff); else if (gpio >= 0x100 && gpio < 0x200) @@ -19,8 +21,10 @@ die("Invalid GPIO"); }
-static void gpio_write_wrapper(u32 gpio, u32 setting) +static void gpio_write_wrapper(u32 iomux_gpio, u32 setting) { + u32 gpio = iomux_gpio << 2; + if (gpio < 0x100) gpio0_write32(gpio & 0xff, setting); else if (gpio >= 0x100 && gpio < 0x200) @@ -29,7 +33,7 @@ gpio2_write32(gpio & 0xff, setting); }
-void configure_gpio(u8 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting) +void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting) { u32 bdata;
@@ -43,7 +47,7 @@ | GPIO_PULL_UP_ENABLE | GPIO_PULL_DOWN_ENABLE)); gpio_write_wrapper(gpio, bdata);
- iomux_write8(iomux_gpio, iomux_ftn & 0x3); + iomux_write8(gpio, iomux_ftn & 0x3); }
u8 read_gpio(u32 gpio) diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 7cc03e8..d1e76de 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -3,48 +3,30 @@ #ifndef GPIO_FTNS_H #define GPIO_FTNS_H
-void configure_gpio(u8 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting); +void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting); u8 read_gpio(u32 gpio); void write_gpio(u32 gpio, u8 value); int get_spd_offset(void);
-#define IOMUX_OFFSET 0xD00 -#define GPIO_OFFSET 0x1500 - // // Based on PC Engines APU2C and APU3A schematics // http://www.pcengines.ch/schema/apu2c.pdf // http://www.pcengines.ch/schema/apu3a.pdf // -#define IOMUX_GPIO_22 0x09 // MODESW (APU5) -#define IOMUX_GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5) -#define IOMUX_GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5) -#define IOMUX_GPIO_49 0x40 // STRAP0 -#define IOMUX_GPIO_50 0x41 // STRAP1 -#define IOMUX_GPIO_51 0x42 // PE3 Reset (SIM1 Reset on APU5) -#define IOMUX_GPIO_55 0x43 // PE4 Reset (SIM2 Reset on APU5) -#define IOMUX_GPIO_57 0x44 // LED1# -#define IOMUX_GPIO_58 0x45 // LED2# -#define IOMUX_GPIO_59 0x46 // LED3# -#define IOMUX_GPIO_64 0x47 // PE3_WDIS (SIM3 Reset on APU5) -#define IOMUX_GPIO_66 0x5B // SPKR -#define IOMUX_GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5) -#define IOMUX_GPIO_71 0x4D // PROCHOT - -#define GPIO_22 0x24 // MODESW (APU5) -#define GPIO_32 0x164 // MODESW (SIMSWAP2 on APU5) -#define GPIO_33 0x168 // SIMSWAP (SIMSWAP3 on APU5) -#define GPIO_49 0x100 // STRAP0 -#define GPIO_50 0x104 // STRAP1 -#define GPIO_51 0x108 // PE3 Reset (SIM1 Reset on APU5) -#define GPIO_55 0x10C // PE4 Reset (SIM2 Reset on APU5) -#define GPIO_57 0x110 // LED1# -#define GPIO_58 0x114 // LED2# -#define GPIO_59 0x118 // LED3# -#define GPIO_64 0x11C // PE3_WDIS (SIM3 Reset on APU5) -#define GPIO_66 0x16C // SPKR -#define GPIO_68 0x120 // PE4_WDIS (SIMSWAP1 on APU5) -#define GPIO_71 0x134 // PROCHOT +#define GPIO_22 0x09 // MODESW (APU5) +#define GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5) +#define GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5) +#define GPIO_49 0x40 // STRAP0 +#define GPIO_50 0x41 // STRAP1 +#define GPIO_51 0x42 // PE3 Reset (SIM1 Reset on APU5) +#define GPIO_55 0x43 // PE4 Reset (SIM2 Reset on APU5) +#define GPIO_57 0x44 // LED1# +#define GPIO_58 0x45 // LED2# +#define GPIO_59 0x46 // LED3# +#define GPIO_64 0x47 // PE3_WDIS (SIM3 Reset on APU5) +#define GPIO_66 0x5B // SPKR +#define GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5) +#define GPIO_71 0x4D // PROCHOT
#define GPIO_OUTPUT_ENABLE BIT23 #define GPIO_OUTPUT_VALUE BIT22 diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index d098bee..0fc472f 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -36,18 +36,18 @@ // Configure output disabled, value low, pull up/down disabled // if (CONFIG(BOARD_PCENGINES_APU5)) { - configure_gpio(IOMUX_GPIO_22, Function0, GPIO_22, setting); + configure_gpio(GPIO_22, Function0, setting); }
if (CONFIG(BOARD_PCENGINES_APU2) || CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4)) { - configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting); + configure_gpio(GPIO_32, Function0, setting); }
- configure_gpio(IOMUX_GPIO_49, Function2, GPIO_49, setting); - configure_gpio(IOMUX_GPIO_50, Function2, GPIO_50, setting); - configure_gpio(IOMUX_GPIO_71, Function0, GPIO_71, setting); + configure_gpio(GPIO_49, Function2, setting); + configure_gpio(GPIO_50, Function2, setting); + configure_gpio(GPIO_71, Function0, setting);
// // Configure output enabled, value low, pull up/down disabled @@ -55,12 +55,12 @@ setting = GPIO_OUTPUT_ENABLE; if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4)) { - configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting); + configure_gpio(GPIO_33, Function0, setting); }
- configure_gpio(IOMUX_GPIO_57, Function1, GPIO_57, setting); - configure_gpio(IOMUX_GPIO_58, Function1, GPIO_58, setting); - configure_gpio(IOMUX_GPIO_59, Function3, GPIO_59, setting); + configure_gpio(GPIO_57, Function1, setting); + configure_gpio(GPIO_58, Function1, setting); + configure_gpio(GPIO_59, Function3, setting);
// // Configure output enabled, value high, pull up/down disabled @@ -68,12 +68,12 @@ setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE;
if (CONFIG(BOARD_PCENGINES_APU5)) { - configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting); - configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting); + configure_gpio(GPIO_32, Function0, setting); + configure_gpio(GPIO_33, Function0, setting); }
- configure_gpio(IOMUX_GPIO_51, Function2, GPIO_51, setting); - configure_gpio(IOMUX_GPIO_55, Function3, GPIO_55, setting); - configure_gpio(IOMUX_GPIO_64, Function2, GPIO_64, setting); - configure_gpio(IOMUX_GPIO_68, Function0, GPIO_68, setting); + configure_gpio(GPIO_51, Function2, setting); + configure_gpio(GPIO_55, Function3, setting); + configure_gpio(GPIO_64, Function2, setting); + configure_gpio(GPIO_68, Function0, setting); }
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42038 )
Change subject: mb/pcengines/apu2: Change GPIO configuration functions ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42038 )
Change subject: mb/pcengines/apu2: Change GPIO configuration functions ......................................................................
mb/pcengines/apu2: Change GPIO configuration functions
The definitions of GPIO_xx equal IOMUX_GPIO_xx shifted by two.
Change-Id: I0ee821c71c88bf535122a9526862a9d1e68bd755 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42038 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/gpio_ftns.h M src/mainboard/pcengines/apu2/romstage.c 3 files changed, 38 insertions(+), 52 deletions(-)
Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index 1969a88..c249c2d 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -7,8 +7,10 @@ #include <FchPlatform.h> #include "gpio_ftns.h"
-static u32 gpio_read_wrapper(u32 gpio) +static u32 gpio_read_wrapper(u32 iomux_gpio) { + u32 gpio = iomux_gpio << 2; + if (gpio < 0x100) return gpio0_read32(gpio & 0xff); else if (gpio >= 0x100 && gpio < 0x200) @@ -19,8 +21,10 @@ die("Invalid GPIO"); }
-static void gpio_write_wrapper(u32 gpio, u32 setting) +static void gpio_write_wrapper(u32 iomux_gpio, u32 setting) { + u32 gpio = iomux_gpio << 2; + if (gpio < 0x100) gpio0_write32(gpio & 0xff, setting); else if (gpio >= 0x100 && gpio < 0x200) @@ -29,7 +33,7 @@ gpio2_write32(gpio & 0xff, setting); }
-void configure_gpio(u8 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting) +void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting) { u32 bdata;
@@ -43,7 +47,7 @@ | GPIO_PULL_UP_ENABLE | GPIO_PULL_DOWN_ENABLE)); gpio_write_wrapper(gpio, bdata);
- iomux_write8(iomux_gpio, iomux_ftn & 0x3); + iomux_write8(gpio, iomux_ftn & 0x3); }
u8 read_gpio(u32 gpio) diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 7cc03e8..d1e76de 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -3,48 +3,30 @@ #ifndef GPIO_FTNS_H #define GPIO_FTNS_H
-void configure_gpio(u8 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting); +void configure_gpio(u32 gpio, u8 iomux_ftn, u32 setting); u8 read_gpio(u32 gpio); void write_gpio(u32 gpio, u8 value); int get_spd_offset(void);
-#define IOMUX_OFFSET 0xD00 -#define GPIO_OFFSET 0x1500 - // // Based on PC Engines APU2C and APU3A schematics // http://www.pcengines.ch/schema/apu2c.pdf // http://www.pcengines.ch/schema/apu3a.pdf // -#define IOMUX_GPIO_22 0x09 // MODESW (APU5) -#define IOMUX_GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5) -#define IOMUX_GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5) -#define IOMUX_GPIO_49 0x40 // STRAP0 -#define IOMUX_GPIO_50 0x41 // STRAP1 -#define IOMUX_GPIO_51 0x42 // PE3 Reset (SIM1 Reset on APU5) -#define IOMUX_GPIO_55 0x43 // PE4 Reset (SIM2 Reset on APU5) -#define IOMUX_GPIO_57 0x44 // LED1# -#define IOMUX_GPIO_58 0x45 // LED2# -#define IOMUX_GPIO_59 0x46 // LED3# -#define IOMUX_GPIO_64 0x47 // PE3_WDIS (SIM3 Reset on APU5) -#define IOMUX_GPIO_66 0x5B // SPKR -#define IOMUX_GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5) -#define IOMUX_GPIO_71 0x4D // PROCHOT - -#define GPIO_22 0x24 // MODESW (APU5) -#define GPIO_32 0x164 // MODESW (SIMSWAP2 on APU5) -#define GPIO_33 0x168 // SIMSWAP (SIMSWAP3 on APU5) -#define GPIO_49 0x100 // STRAP0 -#define GPIO_50 0x104 // STRAP1 -#define GPIO_51 0x108 // PE3 Reset (SIM1 Reset on APU5) -#define GPIO_55 0x10C // PE4 Reset (SIM2 Reset on APU5) -#define GPIO_57 0x110 // LED1# -#define GPIO_58 0x114 // LED2# -#define GPIO_59 0x118 // LED3# -#define GPIO_64 0x11C // PE3_WDIS (SIM3 Reset on APU5) -#define GPIO_66 0x16C // SPKR -#define GPIO_68 0x120 // PE4_WDIS (SIMSWAP1 on APU5) -#define GPIO_71 0x134 // PROCHOT +#define GPIO_22 0x09 // MODESW (APU5) +#define GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5) +#define GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5) +#define GPIO_49 0x40 // STRAP0 +#define GPIO_50 0x41 // STRAP1 +#define GPIO_51 0x42 // PE3 Reset (SIM1 Reset on APU5) +#define GPIO_55 0x43 // PE4 Reset (SIM2 Reset on APU5) +#define GPIO_57 0x44 // LED1# +#define GPIO_58 0x45 // LED2# +#define GPIO_59 0x46 // LED3# +#define GPIO_64 0x47 // PE3_WDIS (SIM3 Reset on APU5) +#define GPIO_66 0x5B // SPKR +#define GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5) +#define GPIO_71 0x4D // PROCHOT
#define GPIO_OUTPUT_ENABLE BIT23 #define GPIO_OUTPUT_VALUE BIT22 diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index d098bee..0fc472f 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -36,18 +36,18 @@ // Configure output disabled, value low, pull up/down disabled // if (CONFIG(BOARD_PCENGINES_APU5)) { - configure_gpio(IOMUX_GPIO_22, Function0, GPIO_22, setting); + configure_gpio(GPIO_22, Function0, setting); }
if (CONFIG(BOARD_PCENGINES_APU2) || CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4)) { - configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting); + configure_gpio(GPIO_32, Function0, setting); }
- configure_gpio(IOMUX_GPIO_49, Function2, GPIO_49, setting); - configure_gpio(IOMUX_GPIO_50, Function2, GPIO_50, setting); - configure_gpio(IOMUX_GPIO_71, Function0, GPIO_71, setting); + configure_gpio(GPIO_49, Function2, setting); + configure_gpio(GPIO_50, Function2, setting); + configure_gpio(GPIO_71, Function0, setting);
// // Configure output enabled, value low, pull up/down disabled @@ -55,12 +55,12 @@ setting = GPIO_OUTPUT_ENABLE; if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4)) { - configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting); + configure_gpio(GPIO_33, Function0, setting); }
- configure_gpio(IOMUX_GPIO_57, Function1, GPIO_57, setting); - configure_gpio(IOMUX_GPIO_58, Function1, GPIO_58, setting); - configure_gpio(IOMUX_GPIO_59, Function3, GPIO_59, setting); + configure_gpio(GPIO_57, Function1, setting); + configure_gpio(GPIO_58, Function1, setting); + configure_gpio(GPIO_59, Function3, setting);
// // Configure output enabled, value high, pull up/down disabled @@ -68,12 +68,12 @@ setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE;
if (CONFIG(BOARD_PCENGINES_APU5)) { - configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting); - configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting); + configure_gpio(GPIO_32, Function0, setting); + configure_gpio(GPIO_33, Function0, setting); }
- configure_gpio(IOMUX_GPIO_51, Function2, GPIO_51, setting); - configure_gpio(IOMUX_GPIO_55, Function3, GPIO_55, setting); - configure_gpio(IOMUX_GPIO_64, Function2, GPIO_64, setting); - configure_gpio(IOMUX_GPIO_68, Function0, GPIO_68, setting); + configure_gpio(GPIO_51, Function2, setting); + configure_gpio(GPIO_55, Function3, setting); + configure_gpio(GPIO_64, Function2, setting); + configure_gpio(GPIO_68, Function0, setting); }
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42038 )
Change subject: mb/pcengines/apu2: Change GPIO configuration functions ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/5239 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5238 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/5237 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/5236
Please note: This test is under development and might not be accurate at all!