Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration

[Angel Pons (Code Review)]

Attention is currently required from: Marc Jones, Subrata Banik, Tim Wawrzynczak, Arthur Heymans, Eric Lai, Lean Sheng Tan.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63630 )

Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
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Patch Set 4:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/63630/comment/76331b48_d59c4904 
PS4, Line 14: configuration register offset 0xDC bits BILD and LE are set.
Could you please test what happens after setting the WPD bit from the OS? For example, using setpci:

sudo setpci -s 0:1f.0 0xdc.b=0x0a

I ask because I had troubles with the SPI PCI device where the SMI handler would fail to clear the SMI source, and the system would hang (it would be stuck in a SMI storm). See CB:50754 for the fix. I don't think this issue can happen with LPC, but I'd appreciate if you could test just to make sure.

File src/soc/intel/common/pch/lockdown/lockdown.c:

https://review.coreboot.org/c/coreboot/+/63630/comment/ca501f06_f0ce657e 
PS4, Line 94: static void lpc_lockdown_config(int chipset_lockdown)
Hmmm, how do the LPC "write protect" bits work, given that the SPI PCI device also has equivalent bits? Do they do anything?