Change in coreboot[master]: arch/x86: Change smm_subregion() prototype

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34706 )

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

arch/x86: Change smm_subregion() prototype

Do this to avoid some amount of explicit typecasting
that would be required otherwise.

Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/x86/smm/stage_cache.c
M src/include/cpu/x86/smm.h
M src/soc/amd/picasso/cpu.c
M src/soc/amd/picasso/ramtop.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/smmrelocate.c
17 files changed, 65 insertions(+), 119 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34706/1

diff --git a/src/cpu/x86/smm/stage_cache.c b/src/cpu/x86/smm/stage_cache.c
index 7806290..3960083 100644
--- a/src/cpu/x86/smm/stage_cache.c
+++ b/src/cpu/x86/smm/stage_cache.c
@@ -25,7 +25,7 @@

void __weak stage_cache_external_region(void **base, size_t *size)
 {
-	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+	if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) {
    	printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
    	*base = NULL;
    	*size = 0;
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 9e631b8..b8b99ec 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -587,7 +587,7 @@
  * Fills in the arguments for the entire SMM region covered by chipset
  * protections. e.g. TSEG.
  */
-void smm_region(void **start, size_t *size);
+void smm_region(uintptr_t *start, size_t *size);

enum {
    /* SMM handler area. */
@@ -602,6 +602,6 @@

/* Fills in the start and size for the requested SMM subregion. Returns
  * 0 on success, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
+int smm_subregion(int sub, uintptr_t *start, size_t *size);

#endif /* CPU_X86_SMM_H */
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index c1d2aff..5c2ca43 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -63,21 +63,21 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;

/* Initialize global tracking state. */
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);

-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.tseg_base = relo_attrs.smbase;
    relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
    relo_attrs.tseg_mask |= SMM_TSEG_WB;

-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
 }
diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c
index 2a0f33d..f936dfc 100644
--- a/src/soc/amd/picasso/ramtop.c
+++ b/src/soc/amd/picasso/ramtop.c
@@ -82,9 +82,9 @@
    return CONFIG_SMM_TSEG_SIZE;
 }

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)smm_region_start();
+	*start = smm_region_start();
    *size = smm_region_size();
 }

@@ -110,15 +110,13 @@
    wrmsr(SMM_MASK_MSR, mask);
 }

-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
    assert(sub_size > CONFIG_SMM_RESERVED_SIZE);

switch (sub) {
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 26d9f7f..4684aea 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -63,21 +63,21 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;

/* Initialize global tracking state. */
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);

-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.tseg_base = relo_attrs.smbase;
    relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
    relo_attrs.tseg_mask |= SMM_TSEG_WB;

-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
 }
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index 2a0f33d..de643cb 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -82,9 +82,9 @@
    return CONFIG_SMM_TSEG_SIZE;
 }

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)smm_region_start();
+	*start = smm_region_start();
    *size = smm_region_size();
 }

@@ -110,15 +110,13 @@
    wrmsr(SMM_MASK_MSR, mask);
 }

-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
    assert(sub_size > CONFIG_SMM_RESERVED_SIZE);

switch (sub) {
@@ -136,8 +134,7 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index f402dfe..9b9b722 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -205,9 +205,9 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;

/* All range registers are aligned to 4KiB */
@@ -217,12 +217,12 @@
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);

-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
    relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
    relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;

-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 3daac3c..7494481 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -43,23 +43,19 @@
    return tolum;
 }

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }

-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
-
-	assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
+	smm_region(&sub_base, &sub_size);

switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -75,8 +71,7 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index 69bbe58..ab1d6f8 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -28,7 +28,7 @@
    return smm_size;
 }

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
    *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20);
    *size = smm_region_size();
@@ -43,15 +43,13 @@
  *     |         (TSEG)          |
  *     +-------------------------+ BUNIT_SMRRL
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
-	void *sub_ptr;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	smm_region(&sub_ptr, &sub_size);
-	sub_base = (uintptr_t)sub_ptr;
+	smm_region(&sub_base, &sub_size);

switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -67,15 +65,14 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }

void *cbmem_top(void)
 {
-	char *smm_base;
+	uintptr_t *smm_base;
    size_t smm_size;

/*
@@ -106,6 +103,6 @@
     *     +-------------------------+
    */

-	smm_region((void **)&smm_base, &smm_size);
+	smm_region(&smm_base, &smm_size);
    return (void *)smm_base;
 }
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 18ddeee..b5b538c 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -29,9 +29,9 @@

#include "chip.h"

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }

@@ -46,16 +46,14 @@
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t ied_size = CONFIG_IED_REGION_SIZE;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);

switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -77,9 +75,8 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }

diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 3ee94e7..67c603a 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -173,10 +173,6 @@

static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
    void *tseg_base;
    size_t tseg_size;
    u32 emrr_base;
@@ -192,14 +188,8 @@
    phys_bits = cpu_phys_address_size();

smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
    params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index d6ddcc0..067f59f 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -126,9 +126,9 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    		 size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;

/* All range registers are aligned to 4KiB */
@@ -138,12 +138,12 @@
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);

-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
    relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
    relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;

-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index d94d1f3..3d750c7 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -70,21 +70,19 @@
    return system_agent_region_base(TOLUD) - smm_region_start();
 }

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
    *start = (void *)smm_region_start();
    *size = smm_region_size();
 }

-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
    assert(sub_size > CONFIG_SMM_RESERVED_SIZE);

switch (sub) {
@@ -101,8 +99,7 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 317f0fb..046774f 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -27,9 +27,9 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }

@@ -44,16 +44,14 @@
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t ied_size = CONFIG_IED_REGION_SIZE;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);

switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -75,9 +73,8 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }

diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index 9630844..a93fa97 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -172,10 +172,6 @@

static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
    void *tseg_base;
    size_t tseg_size;
    u32 emrr_base;
@@ -191,14 +187,8 @@
    phys_bits = cpu_phys_address_size();

smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
    params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index f69a88b..d6ab908 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -25,14 +25,15 @@
 #include <intelblocks/systemagent.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
+#include <soc/smm.h>
 #include <soc/systemagent.h>
 #include <stdlib.h>

#include "chip.h"

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }

@@ -47,16 +48,14 @@
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t ied_size = CONFIG_IED_REGION_SIZE;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);

switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -78,9 +77,8 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }

diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 6e2cf98..828ea4f 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -182,10 +182,6 @@

static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
    void *tseg_base;
    size_t tseg_size;
    u32 emrr_base;
@@ -201,14 +197,8 @@
    phys_bits = cpuid_eax(0x80000008) & 0xff;

smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
    params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;

[Kyösti Mälkki (Code Review)]

Hello Patrick Rudolph, Vanny E, build bot (Jenkins), David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34706

to look at the new patch set (#2).

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

arch/x86: Change smm_subregion() prototype

Do this to avoid some amount of explicit typecasting
that would be required otherwise.

Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/x86/smm/stage_cache.c
M src/include/cpu/x86/smm.h
M src/soc/amd/picasso/cpu.c
M src/soc/amd/picasso/ramtop.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/smmrelocate.c
20 files changed, 77 insertions(+), 131 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34706/2

[Kyösti Mälkki (Code Review)]

Hello Patrick Rudolph, Vanny E, build bot (Jenkins), David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34706

to look at the new patch set (#3).

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

arch/x86: Change smm_subregion() prototype

Do this to avoid some amount of explicit typecasting
that would be required otherwise.

Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/x86/smm/stage_cache.c
M src/include/cpu/x86/smm.h
M src/soc/amd/picasso/cpu.c
M src/soc/amd/picasso/ramtop.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/smmrelocate.c
20 files changed, 78 insertions(+), 132 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34706/3

[Kyösti Mälkki (Code Review)]

Hello Patrick Rudolph, Vanny E, build bot (Jenkins), David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34706

to look at the new patch set (#4).

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

arch/x86: Change smm_subregion() prototype

Do this to avoid some amount of explicit typecasting
that would be required otherwise.

Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/x86/smm/stage_cache.c
M src/drivers/intel/fsp1_1/raminit.c
M src/include/cpu/x86/smm.h
M src/soc/amd/picasso/cpu.c
M src/soc/amd/picasso/ramtop.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/smmrelocate.c
24 files changed, 97 insertions(+), 157 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34706/4

[Kyösti Mälkki (Code Review)]

Hello Patrick Rudolph, Vanny E, Huang Jin, Lee Leahy, build bot (Jenkins), David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34706

to look at the new patch set (#5).

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

arch/x86: Change smm_subregion() prototype

Do this to avoid some amount of explicit typecasting
that would be required otherwise.

Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki 
---
M src/cpu/x86/smm/stage_cache.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/include/cpu/x86/smm.h
M src/soc/amd/picasso/cpu.c
M src/soc/amd/picasso/ramtop.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/braswell/cpu.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/smmrelocate.c
29 files changed, 110 insertions(+), 174 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34706/5

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34706 )

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

Patch Set 5: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34706 )

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34706/7/src/soc/intel/cannonlake/in... 
File src/soc/intel/cannonlake/include/soc/smm.h:

https://review.coreboot.org/c/coreboot/+/34706/7/src/soc/intel/cannonlake/in... 
PS7, Line 32: 
Is there a reason why this was chosen to be fixed width before?

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34706 )

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34706/7/src/soc/intel/cannonlake/in... 
File src/soc/intel/cannonlake/include/soc/smm.h:

https://review.coreboot.org/c/coreboot/+/34706/7/src/soc/intel/cannonlake/in... 
PS7, Line 32:
> Is there a reason why this was chosen to be fixed width before?

Probably just implementation date somewhere 2012 when uintptr_t was not so well known.

BTW CB:34747 removes the smram_ fields and same might be possible with ied_.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34706 )

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34706/7/src/soc/intel/cannonlake/in... 
File src/soc/intel/cannonlake/include/soc/smm.h:

https://review.coreboot.org/c/coreboot/+/34706/7/src/soc/intel/cannonlake/in... 
PS7, Line 32:
> Probably just implementation date somewhere 2012 when uintptr_t was not so well known. […]

Ack.

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34706 )

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34706/7/src/soc/intel/cannonlake/in... 
File src/soc/intel/cannonlake/include/soc/smm.h:

https://review.coreboot.org/c/coreboot/+/34706/7/src/soc/intel/cannonlake/in... 
PS7, Line 32:
> Ack.

Ack

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34706 )

Change subject: arch/x86: Change smm_subregion() prototype
......................................................................

arch/x86: Change smm_subregion() prototype

Do this to avoid some amount of explicit typecasting
that would be required otherwise.

Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/cpu/x86/smm/stage_cache.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
M src/include/cpu/x86/smm.h
M src/soc/amd/picasso/cpu.c
M src/soc/amd/picasso/ramtop.c
M src/soc/amd/picasso/romstage.c
M src/soc/amd/stoneyridge/cpu.c
M src/soc/amd/stoneyridge/ramtop.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/braswell/cpu.c
M src/soc/intel/braswell/memmap.c
M src/soc/intel/braswell/northcluster.c
M src/soc/intel/cannonlake/include/soc/smm.h
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/icelake/include/soc/smm.h
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/include/soc/smm.h
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/smmrelocate.c
29 files changed, 110 insertions(+), 174 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/cpu/x86/smm/stage_cache.c b/src/cpu/x86/smm/stage_cache.c
index 7806290..0a816ba 100644
--- a/src/cpu/x86/smm/stage_cache.c
+++ b/src/cpu/x86/smm/stage_cache.c
@@ -18,14 +18,14 @@
 #include <stage_cache.h>
 #include <types.h>

-int __weak smm_subregion(int sub, void **base, size_t *size)
+int __weak smm_subregion(int sub, uintptr_t *base, size_t *size)
 {
    return -1;
 }

void __weak stage_cache_external_region(void **base, size_t *size)
 {
-	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+	if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) {
    	printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
    	*base = NULL;
    	*size = 0;
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 2f53957..7b893d2 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -53,7 +53,7 @@
    UPD_DATA_REGION *upd_ptr;
    int fsp_verification_failure = 0;
    EFI_PEI_HOB_POINTERS hob_ptr;
-	char *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;

/*
@@ -148,9 +148,9 @@

/* Display SMM area */
    if (CONFIG(HAVE_SMI_HANDLER)) {
-		smm_region((void **)&smm_base, &smm_size);
+		smm_region(&smm_base, &smm_size);
    	printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size);
-		printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base);
+		printk(BIOS_DEBUG, "0x%08x: smm_base\n", (unsigned int)smm_base);
    }

/* Migrate CAR data */
@@ -238,7 +238,7 @@
    	printk(BIOS_ERR, "ERROR - Reserving FSP memory area!\n");

if (CONFIG(HAVE_SMI_HANDLER) && cbmem_root != NULL) {
-			size_t delta_bytes = (unsigned int)smm_base
+			size_t delta_bytes = smm_base
    			- cbmem_root->PhysicalStart
    			- cbmem_root->ResourceLength;
    		printk(BIOS_ERR,
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 049dfd0..4b567da 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -33,19 +33,19 @@
 /* Display SMM memory map */
 static void smm_memory_map(void)
 {
-	void *base;
+	uintptr_t base;
    size_t size;
    int i;

printk(BIOS_SPEW, "SMM Memory Map\n");

smm_region(&base, &size);
-	printk(BIOS_SPEW, "SMRAM       : %p 0x%zx\n", base, size);
+	printk(BIOS_SPEW, "SMRAM       : 0x%zx 0x%zx\n", base, size);

for (i = 0; i < SMM_SUBREGION_NUM; i++) {
    	if (smm_subregion(i, &base, &size))
    		continue;
-		printk(BIOS_SPEW, " Subregion %d: %p 0x%zx\n", i, base, size);
+		printk(BIOS_SPEW, " Subregion %d: 0x%zx 0x%zx\n", i, base, size);
    }
 }

diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 9e631b8..b8b99ec 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -587,7 +587,7 @@
  * Fills in the arguments for the entire SMM region covered by chipset
  * protections. e.g. TSEG.
  */
-void smm_region(void **start, size_t *size);
+void smm_region(uintptr_t *start, size_t *size);

enum {
    /* SMM handler area. */
@@ -602,6 +602,6 @@

/* Fills in the start and size for the requested SMM subregion. Returns
  * 0 on success, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
+int smm_subregion(int sub, uintptr_t *start, size_t *size);

#endif /* CPU_X86_SMM_H */
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index c1d2aff..5c2ca43 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -63,21 +63,21 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;

/* Initialize global tracking state. */
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);

-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.tseg_base = relo_attrs.smbase;
    relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
    relo_attrs.tseg_mask |= SMM_TSEG_WB;

-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
 }
diff --git a/src/soc/amd/picasso/ramtop.c b/src/soc/amd/picasso/ramtop.c
index f0051e4..344b7f7 100644
--- a/src/soc/amd/picasso/ramtop.c
+++ b/src/soc/amd/picasso/ramtop.c
@@ -81,9 +81,9 @@
    return CONFIG_SMM_TSEG_SIZE;
 }

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)smm_region_start();
+	*start = smm_region_start();
    *size = smm_region_size();
 }

@@ -109,15 +109,13 @@
    wrmsr(SMM_MASK_MSR, mask);
 }

-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
    assert(sub_size > CONFIG_SMM_RESERVED_SIZE);

switch (sub) {
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 64c18d2..dae64cc 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -43,9 +43,8 @@
 {
    struct postcar_frame pcf;
    uintptr_t top_of_ram;
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	uintptr_t tseg_base;
    int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3();

console_init();
@@ -92,8 +91,7 @@
     * region for other purposes.
     */
    smm_region(&smm_base, &smm_size);
-	tseg_base = (uintptr_t)smm_base;
-	postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);

post_code(0x45);
    run_postcar_phase(&pcf);
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 26d9f7f..4684aea 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -63,21 +63,21 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;

/* Initialize global tracking state. */
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);

-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.tseg_base = relo_attrs.smbase;
    relo_attrs.tseg_mask = ALIGN_DOWN(~(smm_size - 1), 128 * KiB);
    relo_attrs.tseg_mask |= SMM_TSEG_WB;

-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
 }
diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c
index f0051e4..3a23df6 100644
--- a/src/soc/amd/stoneyridge/ramtop.c
+++ b/src/soc/amd/stoneyridge/ramtop.c
@@ -81,9 +81,9 @@
    return CONFIG_SMM_TSEG_SIZE;
 }

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)smm_region_start();
+	*start = smm_region_start();
    *size = smm_region_size();
 }

@@ -109,15 +109,13 @@
    wrmsr(SMM_MASK_MSR, mask);
 }

-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
    assert(sub_size > CONFIG_SMM_RESERVED_SIZE);

switch (sub) {
@@ -135,8 +133,7 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 3c97e5e..42b0833 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -84,9 +84,8 @@
 {
    struct postcar_frame pcf;
    uintptr_t top_of_ram;
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	uintptr_t tseg_base;
    msr_t base, mask;
    msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
    int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
@@ -177,8 +176,7 @@
     * region for other purposes.
     */
    smm_region(&smm_base, &smm_size);
-	tseg_base = (uintptr_t)smm_base;
-	postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);

post_code(0x45);
    run_postcar_phase(&pcf);
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index f402dfe..9b9b722 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -205,9 +205,9 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;

/* All range registers are aligned to 4KiB */
@@ -217,12 +217,12 @@
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);

-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
    relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
    relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;

-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 3daac3c..7494481 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -43,23 +43,19 @@
    return tolum;
 }

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }

-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
-
-	assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
+	smm_region(&sub_base, &sub_size);

switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -75,8 +71,7 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 62eb1db..3ce6370 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -202,10 +202,9 @@
    uintptr_t top_of_ram;
    bool s3wake;
    struct chipset_power_state *ps = pmc_get_power_state();
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size, var_size;
    const void *new_var_data;
-	uintptr_t tseg_base;

timestamp_add_now(TS_START_ROMSTAGE);

@@ -258,8 +257,7 @@
    * region for other purposes.
    */
    smm_region(&smm_base, &smm_size);
-	tseg_base = (uintptr_t)smm_base;
-	postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);

run_postcar_phase(&pcf);
 }
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index bde4b1c..1cee4b9 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -150,7 +150,7 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;

/* All range registers are aligned to 4KiB */
@@ -158,7 +158,7 @@

/* Initialize global tracking state. */
    smm_region(&smm_base, &smm_size);
-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
    relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
    relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index 69bbe58..01594ea 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -28,9 +28,9 @@
    return smm_size;
 }

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20);
+	*start = (iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20;
    *size = smm_region_size();
 }

@@ -43,15 +43,13 @@
  *     |         (TSEG)          |
  *     +-------------------------+ BUNIT_SMRRL
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
-	void *sub_ptr;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	smm_region(&sub_ptr, &sub_size);
-	sub_base = (uintptr_t)sub_ptr;
+	smm_region(&sub_base, &sub_size);

switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -67,15 +65,14 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }

void *cbmem_top(void)
 {
-	char *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;

/*
@@ -106,6 +103,6 @@
     *     +-------------------------+
    */

-	smm_region((void **)&smm_base, &smm_size);
+	smm_region(&smm_base, &smm_size);
    return (void *)smm_base;
 }
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index e37e0d6..ff58ebf 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -87,7 +87,7 @@
    unsigned long mmconf;
    unsigned long bmbound_k;
    unsigned long bmbound_hi;
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
    unsigned long tseg_base_k;
    unsigned long tseg_top_k;
@@ -102,7 +102,7 @@

/* Determine TSEG data */
    smm_region(&smm_base, &smm_size);
-	tseg_base_k = RES_IN_KIB((unsigned long) smm_base);
+	tseg_base_k = RES_IN_KIB(smm_base);
    tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size);

/* Determine the base of the FSP reserved memory */
diff --git a/src/soc/intel/cannonlake/include/soc/smm.h b/src/soc/intel/cannonlake/include/soc/smm.h
index bf58b9c..5f51fa2 100644
--- a/src/soc/intel/cannonlake/include/soc/smm.h
+++ b/src/soc/intel/cannonlake/include/soc/smm.h
@@ -29,10 +29,10 @@
 } __packed;

struct smm_relocation_params {
-	u32 smram_base;
-	u32 smram_size;
-	u32 ied_base;
-	u32 ied_size;
+	uintptr_t smram_base;
+	size_t smram_size;
+	uintptr_t ied_base;
+	size_t ied_size;
    msr_t smrr_base;
    msr_t smrr_mask;
    msr_t emrr_base;
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 18ddeee..b5b538c 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -29,9 +29,9 @@

#include "chip.h"

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }

@@ -46,16 +46,14 @@
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t ied_size = CONFIG_IED_REGION_SIZE;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);

switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -77,9 +75,8 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }

diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index 3ee94e7..ef30078 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -173,11 +173,7 @@

static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
-	void *tseg_base;
+	uintptr_t tseg_base;
    size_t tseg_size;
    u32 emrr_base;
    u32 emrr_size;
@@ -192,14 +188,8 @@
    phys_bits = cpu_phys_address_size();

smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
    params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
@@ -242,8 +232,8 @@

ied_base = (void *)params->ied_base;

-	printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
-	printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
+	printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base);
+	printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size);

/* Place IED header at IEDBASE. */
    memcpy(ied_base, &ied, sizeof(ied));
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index d6ddcc0..067f59f 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -126,9 +126,9 @@
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    		 size_t *smm_save_state_size)
 {
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	void *handler_base;
+	uintptr_t handler_base;
    size_t handler_size;

/* All range registers are aligned to 4KiB */
@@ -138,12 +138,12 @@
    smm_region(&smm_base, &smm_size);
    smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);

-	relo_attrs.smbase = (uint32_t)smm_base;
+	relo_attrs.smbase = smm_base;
    relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
    relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
    relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;

-	*perm_smbase = (uintptr_t)handler_base;
+	*perm_smbase = handler_base;
    *perm_smsize = handler_size;
    *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
 }
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index d94d1f3..d4265e9 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -70,21 +70,19 @@
    return system_agent_region_base(TOLUD) - smm_region_start();
 }

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)smm_region_start();
+	*start = smm_region_start();
    *size = smm_region_size();
 }

-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	sub_base = smm_region_start();
-	sub_size = smm_region_size();
-
+	smm_region(&sub_base, &sub_size);
    assert(sub_size > CONFIG_SMM_RESERVED_SIZE);

switch (sub) {
@@ -101,8 +99,7 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 6950620..53c51f4 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -141,9 +141,8 @@

struct postcar_frame pcf;
    uintptr_t top_of_ram;
-	void *smm_base;
+	uintptr_t smm_base;
    size_t smm_size;
-	uintptr_t tseg_base;

console_init();

@@ -183,8 +182,7 @@
     */
    if (CONFIG(HAVE_SMI_HANDLER)) {
    	smm_region(&smm_base, &smm_size);
-		tseg_base = (uintptr_t)smm_base;
-		postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK);
+		postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
    }

run_postcar_phase(&pcf);
diff --git a/src/soc/intel/icelake/include/soc/smm.h b/src/soc/intel/icelake/include/soc/smm.h
index 75cb4ea..498a221 100644
--- a/src/soc/intel/icelake/include/soc/smm.h
+++ b/src/soc/intel/icelake/include/soc/smm.h
@@ -28,10 +28,10 @@
 } __packed;

struct smm_relocation_params {
-	u32 smram_base;
-	u32 smram_size;
-	u32 ied_base;
-	u32 ied_size;
+	uintptr_t smram_base;
+	size_t smram_size;
+	uintptr_t ied_base;
+	size_t ied_size;
    msr_t smrr_base;
    msr_t smrr_mask;
    msr_t emrr_base;
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 317f0fb..046774f 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -27,9 +27,9 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }

@@ -44,16 +44,14 @@
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t ied_size = CONFIG_IED_REGION_SIZE;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);

switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -75,9 +73,8 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }

diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index 9630844..dfdec22 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -172,11 +172,7 @@

static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
-	void *tseg_base;
+	uintptr_t tseg_base;
    size_t tseg_size;
    u32 emrr_base;
    u32 emrr_size;
@@ -191,14 +187,8 @@
    phys_bits = cpu_phys_address_size();

smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
    params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
@@ -241,8 +231,8 @@

ied_base = (void *)params->ied_base;

-	printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
-	printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
+	printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32)params->ied_base);
+	printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32)params->ied_size);

/* Place IED header at IEDBASE. */
    memcpy(ied_base, &ied, sizeof(ied));
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index 1000ce8..b2debe8 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -30,10 +30,10 @@
 } __packed;

struct smm_relocation_params {
-	u32 smram_base;
-	u32 smram_size;
-	u32 ied_base;
-	u32 ied_size;
+	uintptr_t smram_base;
+	size_t smram_size;
+	uintptr_t ied_base;
+	size_t ied_size;
    msr_t smrr_base;
    msr_t smrr_mask;
    msr_t emrr_base;
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index f69a88b..d6ab908 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -25,14 +25,15 @@
 #include <intelblocks/systemagent.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
+#include <soc/smm.h>
 #include <soc/systemagent.h>
 #include <stdlib.h>

#include "chip.h"

-void smm_region(void **start, size_t *size)
+void smm_region(uintptr_t *start, size_t *size)
 {
-	*start = (void *)sa_get_tseg_base();
+	*start = sa_get_tseg_base();
    *size = sa_get_tseg_size();
 }

@@ -47,16 +48,14 @@
  *     |         (TSEG)          |
  *     +-------------------------+ TSEG
  */
-int smm_subregion(int sub, void **start, size_t *size)
+int smm_subregion(int sub, uintptr_t *start, size_t *size)
 {
    uintptr_t sub_base;
    size_t sub_size;
-	void *smm_base;
    const size_t ied_size = CONFIG_IED_REGION_SIZE;
    const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;

-	smm_region(&smm_base, &sub_size);
-	sub_base = (uintptr_t)smm_base;
+	smm_region(&sub_base, &sub_size);

switch (sub) {
    case SMM_SUBREGION_HANDLER:
@@ -78,9 +77,8 @@
    	return -1;
    }

-	*start = (void *)sub_base;
+	*start = sub_base;
    *size = sub_size;
-
    return 0;
 }

diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index b3781e2..221c6c4 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -173,9 +173,8 @@
    postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);

if (CONFIG(HAVE_SMI_HANDLER)) {
-		void *smm_base;
+		uintptr_t smm_base;
    	size_t smm_size;
-		uintptr_t tseg_base;

/*
    	 * Cache the TSEG region at the top of ram. This region is
@@ -185,8 +184,7 @@
    	 * region for other purposes.
    	 */
    	smm_region(&smm_base, &smm_size);
-		tseg_base = (uintptr_t)smm_base;
-		postcar_frame_add_mtrr(&pcf, tseg_base, smm_size,
+		postcar_frame_add_mtrr(&pcf, smm_base, smm_size,
    				MTRR_TYPE_WRBACK);
    }

diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 6e2cf98..b69692f 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -182,11 +182,7 @@

static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
-	void *handler_base;
-	size_t handler_size;
-	void *ied_base;
-	size_t ied_size;
-	void *tseg_base;
+	uintptr_t tseg_base;
    size_t tseg_size;
    u32 emrr_base;
    u32 emrr_size;
@@ -201,14 +197,8 @@
    phys_bits = cpuid_eax(0x80000008) & 0xff;

smm_region(&tseg_base, &tseg_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
-	smm_subregion(SMM_SUBREGION_CHIPSET, &ied_base, &ied_size);
-
-	params->smram_size = handler_size;
-	params->smram_base = (uintptr_t)handler_base;
-
-	params->ied_base = (uintptr_t)ied_base;
-	params->ied_size = ied_size;
+	smm_subregion(SMM_SUBREGION_HANDLER, &params->smram_base, &params->smram_size);
+	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
    params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
@@ -251,8 +241,8 @@

ied_base = (void *)params->ied_base;

-	printk(BIOS_DEBUG, "IED base = 0x%08x\n", params->ied_base);
-	printk(BIOS_DEBUG, "IED size = 0x%08x\n", params->ied_size);
+	printk(BIOS_DEBUG, "IED base = 0x%08x\n", (u32) params->ied_base);
+	printk(BIOS_DEBUG, "IED size = 0x%08x\n", (u32) params->ied_size);

/* Place IED header at IEDBASE. */
    memcpy(ied_base, &ied, sizeof(ied));