Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Subrata Banik, Paul Menzel, Sridhar Siricilla, Angel Pons, Kane Chen.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )

Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
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Patch Set 7: Code-Review+1

(2 comments)

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63293/comment/2eb27e66_77c05ca1 
PS7, Line 578: 	 * Add Workaround to disable PCH USB2 Phy power gating as per Intel TA# 723158 to
             : 	 * prevent possible display flicker issue.
             : 	 * Enable or Disable PCH USB2 Phy power gating.
             : 	 * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating.
I would add this comment into the mainboard patch, not the SoC code; there could be other valid reasons for this setting this option, unrelated to the TA ?

https://review.coreboot.org/c/coreboot/+/63293/comment/0566d59c_a09c3cba 
PS7, Line 582: 	 *
nit; extra blank line