Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33485
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
mainboard/google/hatch: Scrub Helios GPIOs
Helios has a number of GPIO changes w/r/t to its baseboard. Override early, sleep and normal GPIOs as appropriate.
BUG=b:135257452 BRANCH=none TEST=Compile only (no boards to test with)
Change-Id: I45793ad6515df5af5b925d92106bd943374353d4 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/variants/helios/Makefile.inc A src/mainboard/google/hatch/variants/helios/gpio.c 2 files changed, 131 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33485/1
diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc index cf6ee5a..2f590bf 100644 --- a/src/mainboard/google/hatch/variants/helios/Makefile.inc +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -18,3 +18,6 @@ SPD_SOURCES += 8G_2666 # 0b011 SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 + +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c new file mode 100644 index 0000000..9f39044 --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* H4 : I2C2_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : I2C2_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), + /* H19 : TIMESYNC[0] ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H14 : M2_SKT2_CFG2 ==> TOUCHSCREEN_STOP_L */ + PAD_CFG_TERM_GPO(GPP_H14, 1, UP_20K, PLTRST), + /* H13 : M2_SKT2_CFG1 ==> SPKR_RST_L */ + PAD_CFG_TERM_GPO(GPP_H13, 1, UP_20K, PLTRST), + /* G0 : GPP_G0 ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : GPP_G1 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : GPP_G2 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : GPP_G3 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : GPP_G4 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : GPP_G5 ==> NC */ + PAD_NC(GPP_G5, NONE), + /* G6 : GPP_G6 ==> NC */ + PAD_NC(GPP_G6, NONE), + /* F3 : GPP_F3 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F22 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_F22, NONE), + /* F21 : EMMC_CLK ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F20 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F11 : EMMC_CMD ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F10 : GPP_F10 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F1 : GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* F0 : GPP_F0 ==> NC */ + PAD_NC(GPP_F0, NONE), + /* D8 : ISH_I2C1_SCL ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D7 : ISH_I2C1_SDA ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D6 : ISH_I2C0_SCL ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D5 : ISH_I2C0_SDA ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D21 : SPI1_IO2 ==> NC */ + PAD_NC(GPP_D21, NONE), + /* D10 : ISH_SPI_CLK ==> EN_PP3300_PP1800_FP */ + PAD_CFG_TERM_GPO(GPP_D10, 0, DN_20K, DEEP), + /* C7 : GPP_C7 ==> NC */ + PAD_NC(GPP_C7, NONE), + /* C6 : GPP_C6 ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + /* C15 : UART1_CTS# ==> NC */ + PAD_NC(GPP_C15, NONE), + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* B19 : GSPI1_CS0# ==> NC */ + PAD_NC(GPP_B19, NONE), + /* A6 : SERIRQ ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A20 : ISH_GP2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A19 : ISH_GP1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A18 : ISH_GP0 ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A0 : RCIN# ==> NC */ + PAD_NC(GPP_A0, NONE), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs configured before ramstage */ +static const struct pad_config early_gpio_table[] = { + PAD_NC(GPP_C23, NONE), +}; + +const struct pad_config *override_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* + * GPIO settings before entering all sleep states + */ +static const struct pad_config sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + *num = ARRAY_SIZE(sleep_gpio_table); + return sleep_gpio_table; +}
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33485
to look at the new patch set (#2).
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
mainboard/google/hatch: Scrub Helios GPIOs
Helios has a number of GPIO changes w/r/t to its baseboard. Override early, sleep and normal GPIOs as appropriate.
BUG=b:135257452 BRANCH=none TEST=Compile only (no boards to test with)
Change-Id: I45793ad6515df5af5b925d92106bd943374353d4 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/variants/helios/Makefile.inc A src/mainboard/google/hatch/variants/helios/gpio.c 2 files changed, 130 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33485/2
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33485 )
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
Patch Set 2: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33485 )
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/#/c/33485/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/helios/gpio.c:
https://review.coreboot.org/#/c/33485/2/src/mainboard/google/hatch/variants/... PS2, Line 31: 1 This should eventually be de-asserted in ACPI _ON routine so that the power on timings are not violated. We can leave it here for now.
https://review.coreboot.org/#/c/33485/2/src/mainboard/google/hatch/variants/... PS2, Line 31: UP_20K Why is the pull-up required?
https://review.coreboot.org/#/c/33485/2/src/mainboard/google/hatch/variants/... PS2, Line 33: UP_20K Why is internal pull-up required if we are actively driving it?
https://review.coreboot.org/#/c/33485/2/src/mainboard/google/hatch/variants/... PS2, Line 75: DN_20K Why PD?
Hello Paul Fagerburg, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33485
to look at the new patch set (#3).
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
mainboard/google/hatch: Scrub Helios GPIOs
Helios has a number of GPIO changes w/r/t to its baseboard. Override early, sleep and normal GPIOs as appropriate.
BUG=b:135257452 BRANCH=none TEST=Compile only (no boards to test with)
Change-Id: I45793ad6515df5af5b925d92106bd943374353d4 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/variants/helios/Makefile.inc A src/mainboard/google/hatch/variants/helios/gpio.c 2 files changed, 130 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33485/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33485 )
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/33485/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/helios/gpio.c:
https://review.coreboot.org/#/c/33485/2/src/mainboard/google/hatch/variants/... PS2, Line 31: UP_20K
Why is the pull-up required?
I'm not sure how these are handled at the OS level, so I figured a pull-up was safest.
https://review.coreboot.org/#/c/33485/2/src/mainboard/google/hatch/variants/... PS2, Line 75: DN_20K
Why PD?
I wasn't sure if these needed to be disabled until the OS comes up?
Hello Paul Fagerburg, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33485
to look at the new patch set (#4).
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
mainboard/google/hatch: Scrub Helios GPIOs
Helios has a number of GPIO changes w/r/t to its baseboard. Override early, sleep and normal GPIOs as appropriate.
BUG=b:135257452 BRANCH=none TEST=Compile only (no boards to test with)
Change-Id: I45793ad6515df5af5b925d92106bd943374353d4 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/hatch/variants/helios/Makefile.inc A src/mainboard/google/hatch/variants/helios/gpio.c 2 files changed, 130 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33485/4
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33485 )
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/33485/2/src/mainboard/google/hatch/variants/... File src/mainboard/google/hatch/variants/helios/gpio.c:
https://review.coreboot.org/#/c/33485/2/src/mainboard/google/hatch/variants/... PS2, Line 31: UP_20K
I'm not sure how these are handled at the OS level, so I figured a pull-up was safest.
No, these are being actively driven once configured and so pull-up/down should not be required.
Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33485 )
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
Patch Set 4: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33485 )
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
Patch Set 4: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33485 )
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
Patch Set 4:
Submitting early since this is required for factory build.
Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33485 )
Change subject: mainboard/google/hatch: Scrub Helios GPIOs ......................................................................
mainboard/google/hatch: Scrub Helios GPIOs
Helios has a number of GPIO changes w/r/t to its baseboard. Override early, sleep and normal GPIOs as appropriate.
BUG=b:135257452 BRANCH=none TEST=Compile only (no boards to test with)
Change-Id: I45793ad6515df5af5b925d92106bd943374353d4 Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/33485 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Fagerburg pfagerburg@chromium.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/variants/helios/Makefile.inc A src/mainboard/google/hatch/variants/helios/gpio.c 2 files changed, 130 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Paul Fagerburg: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/helios/Makefile.inc b/src/mainboard/google/hatch/variants/helios/Makefile.inc index ddafa32..fbd69c4 100644 --- a/src/mainboard/google/hatch/variants/helios/Makefile.inc +++ b/src/mainboard/google/hatch/variants/helios/Makefile.inc @@ -16,3 +16,5 @@ SPD_SOURCES += LP_16G_2133 # 0b0001
romstage-y += memory.c +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/helios/gpio.c b/src/mainboard/google/hatch/variants/helios/gpio.c new file mode 100644 index 0000000..4353fc0 --- /dev/null +++ b/src/mainboard/google/hatch/variants/helios/gpio.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A0 : RCIN# ==> NC */ + PAD_NC(GPP_A0, NONE), + /* A6 : SERIRQ ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A18 : ISH_GP0 ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : ISH_GP1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : ISH_GP2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* B19 : GSPI1_CS0# ==> NC */ + PAD_NC(GPP_B19, NONE), + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C6 : GPP_C6 ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C7 : GPP_C7 ==> NC */ + PAD_NC(GPP_C7, NONE), + /* C15 : UART1_CTS# ==> NC */ + PAD_NC(GPP_C15, NONE), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + /* D5 : ISH_I2C0_SDA ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D6 : ISH_I2C0_SCL ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : ISH_I2C1_SDA ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D8 : ISH_I2C1_SCL ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D10 : ISH_SPI_CLK ==> EN_PP3300_PP1800_FP */ + PAD_CFG_GPO(GPP_D10, 0, DEEP), + /* D21 : SPI1_IO2 ==> NC */ + PAD_NC(GPP_D21, NONE), + /* F0 : GPP_F0 ==> NC */ + PAD_NC(GPP_F0, NONE), + /* F1 : GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : GPP_F3 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : GPP_F10 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F20 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EMMC_CLK ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_F22, NONE), + /* G0 : GPP_G0 ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : GPP_G1 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : GPP_G2 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : GPP_G3 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : GPP_G4 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : GPP_G5 ==> NC */ + PAD_NC(GPP_G5, NONE), + /* G6 : GPP_G6 ==> NC */ + PAD_NC(GPP_G6, NONE), + /* H4 : I2C2_SDA ==> NC */ + PAD_NC(GPP_H4, NONE), + /* H5 : I2C2_SCL ==> NC */ + PAD_NC(GPP_H5, NONE), + /* H13 : M2_SKT2_CFG1 ==> SPKR_RST_L */ + PAD_CFG_GPO(GPP_H13, 0, PLTRST), + /* H14 : M2_SKT2_CFG2 ==> TOUCHSCREEN_STOP_L */ + PAD_CFG_GPO(GPP_H14, 0, PLTRST), + /* H19 : TIMESYNC[0] ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs configured before ramstage */ +static const struct pad_config early_gpio_table[] = { + PAD_NC(GPP_C23, NONE), +}; + +const struct pad_config *override_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* + * GPIO settings before entering all sleep states + */ +static const struct pad_config sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + *num = ARRAY_SIZE(sleep_gpio_table); + return sleep_gpio_table; +}
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Furquan Shaikh (Code Review) -
Paul Fagerburg (Code Review)
-
Tim Wawrzynczak (Code Review)