[L] Change in coreboot[main]: vc/intel/fsp2_4: Add UPDs into the FSP partial header version 7148

[Saurabh Mishra (Code Review)]

Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83636?usp=email )

Change subject: vc/intel/fsp2_4: Add UPDs into the FSP partial header version 7148
......................................................................

vc/intel/fsp2_4: Add UPDs into the FSP partial header version 7148

Change-Id: I7ef76d6fc76b2e87daeb44af8df471d20c2e43f6
Signed-off-by: Saurabh Mishra 
---
A src/vendorcode/intel/fsp/fsp2_4/pantherlake/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_4/pantherlake/FspsUpd.h
2 files changed, 405 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/83636/1

diff --git a/src/vendorcode/intel/fsp/fsp2_4/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_4/pantherlake/FspmUpd.h
new file mode 100644
index 0000000..d6c3bb2
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_4/pantherlake/FspmUpd.h
@@ -0,0 +1,265 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+#include <MemInfoHob.h>
+
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+  UINT8             Revision;         ///< Chipset Init Info Revision
+  UINT8             Rsvd[3];          ///< Reserved
+  UINT16            MeChipInitCrc;    ///< 16 bit CRC value of MeChipInit Table
+  UINT16            BiosChipInitCrc;  ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
+
+/** FSP M Configuration
+**/
+typedef struct {
+
+/** Offset 0x0060 - Serial Io Uart Debug Mode
+  Select SerialIo Uart Controller mode
+  0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+  4:SerialIoUartSkipInit
+**/
+  UINT8                       SerialIoUartDebugMode;
+
+/** Offset 0x0061 - Serial Io Uart Debug Auto Flow
+  Enables UART hardware flow control, CTS and RTS lines.
+  $EN_DIS
+**/
+  UINT8                       SerialIoUartDebugAutoFlow;
+
+/** Offset 0x0062 - Reserved
+**/
+  UINT8                       UnusedUpdSpace0[2];
+
+/** Offset 0x0064 - SerialIoUartDebugRxPinMux - FSPT
+  Select RX pin muxing for SerialIo UART used for debug
+**/
+  UINT32                      SerialIoUartDebugRxPinMux;
+
+/** Offset 0x0068 - SerialIoUartDebugTxPinMux - FSPM
+  Select TX pin muxing for SerialIo UART used for debug
+**/
+  UINT32                      SerialIoUartDebugTxPinMux;
+
+/** Offset 0x006C - SerialIoUartDebugRtsPinMux - FSPM
+  Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+  for possible values.
+**/
+  UINT32                      SerialIoUartDebugRtsPinMux;
+
+/** Offset 0x0070 - SerialIoUartDebugCtsPinMux - FSPM
+  Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+  for possible values.
+**/
+  UINT32                      SerialIoUartDebugCtsPinMux;
+
+/** Offset 0x0074 - Platform Debug Option
+  Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
+  \n
+  Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n
+  \n
+  Enabled Trace power off: TraceHub is powergated, provide setting close to functional
+  low power state\n
+  \n
+  Manual: user needs to configure Advanced Debug Settings manually, aimed at advanced users
+  0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready, 6:Enable Trace Power-Off, 7:Manual
+**/
+  UINT8                       PlatformDebugOption;
+
+/** Offset 0x0075 - Debug Interfaces
+  Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+  BIT2 - Not used.
+**/
+  UINT8                       PcdDebugInterfaceFlags;
+
+/** Offset 0x0076 - Reserved
+**/
+  UINT8                       UnusedUpdSpace1[2];
+
+/** Offset 0x0078 - Reserved
+**/
+  UINT64                      TdxActmModuleAddr;
+
+/** Offset 0x0080 - Reserved
+**/
+  UINT32                      TdxActmModuleSize;
+
+/** Offset 0x0084 - PcdSerialDebugLevel
+  Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+  Info & Verbose.
+  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+  Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+  UINT8                       PcdSerialDebugLevel;
+
+/** Offset 0x0085 - SerialDebugMrcLevel
+  MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+  Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+  Info & Verbose.
+  0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+  Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+  UINT8                       SerialDebugMrcLevel;
+
+/** Offset 0x0086 - Serial Io Uart Debug Controller Number
+  Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+  Core interface, it cannot be used for debug purpose.
+  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+  UINT8                       SerialIoUartDebugControllerNumber;
+
+/** Offset 0x0087 - Serial Io Uart Debug Parity
+  Set default Parity.
+  0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+  UINT8                       SerialIoUartDebugParity;
+
+/** Offset 0x0088 - Serial Io Uart Debug BaudRate
+  Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
+  19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
+**/
+  UINT32                      SerialIoUartDebugBaudRate;
+
+/** Offset 0x008C - Serial Io Uart Debug Stop Bits
+  Set default stop bits.
+  0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+  UINT8                       SerialIoUartDebugStopBits;
+
+/** Offset 0x008D - Serial Io Uart Debug Data Bits
+  Set default word length. 0: Default, 5,6,7,8
+  5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
+**/
+  UINT8                       SerialIoUartDebugDataBits;
+
+/** Offset 0x008E - ISA Serial Base selection
+  Select ISA Serial Base address. Default is 0x3F8.
+  0:0x3F8, 1:0x2F8
+**/
+  UINT8                       PcdIsaSerialUartBase;
+
+/** Offset 0x008F - PcdSerialDebugBaudRate
+  Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
+  3:9600, 4:19200, 6:56700, 7:115200
+**/
+  UINT8                       PcdSerialDebugBaudRate;
+
+/** Offset 0x0090 - Post Code Output Port
+  This option configures Post Code Output Port
+**/
+  UINT16                      PostCodeOutputPort;
+
+/** Offset 0x0092 - Reserved
+**/
+  UINT8                       I2cPostCodeEnable;
+
+/** Offset 0x0093 - TCSS USB HOST (xHCI) Enable
+  Set TCSS XHCI. 0:Disabled  1:Enabled - Must be enabled if xDCI is enabled below
+  $EN_DIS
+**/
+  UINT8                       TcssXhciEn;
+
+/** Offset 0x0094 - Reserved
+**/
+  UINT8                       UnusedUpdSpace2[1];
+
+/** Offset 0x0095 - Reserved
+**/
+  UINT8                       ReservedFspmUpd[3];
+} FSP_M_CONFIG;
+
+/** Fsp M Restricted Configuration
+**/
+typedef struct {
+
+/** Offset 0x0098 - Reserved
+**/
+  UINT32                      Signature;
+
+/** Offset 0x009C - Reserved
+**/
+  UINT8                       DisableResets;
+
+/** Offset 0x009D - Reserved
+**/
+  UINT8                       UnusedUpdSpace3[1];
+
+/** Offset 0x009E - Reserved
+**/
+  UINT8                       ReservedFspmRestrictedUpd[2];
+} FSP_M_RESTRICTED_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSPM_ARCH2_UPD              FspmArchUpd;
+
+/** Offset 0x0060
+**/
+  FSP_M_CONFIG                FspmConfig;
+
+/** Offset 0x0098
+**/
+  FSP_M_RESTRICTED_CONFIG     FspmRestrictedConfig;
+
+/** Offset 0x00A0
+**/
+  UINT8                       UnusedUpdSpace4[6];
+
+/** Offset 0x00A6
+**/
+  UINT16                      UpdTerminator;
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_4/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_4/pantherlake/FspsUpd.h
new file mode 100644
index 0000000..3e7edac
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_4/pantherlake/FspsUpd.h
@@ -0,0 +1,140 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+
+///
+/// Azalia Header structure
+///
+typedef struct {
+  UINT16 VendorId;           ///< Codec Vendor ID
+  UINT16 DeviceId;           ///< Codec Device ID
+  UINT8  RevisionId;         ///< Revision ID of the codec. 0xFF matches any revision.
+  UINT8  SdiNum;             ///< SDI number, 0xFF matches any SDI.
+  UINT16 DataDwords;         ///< Number of data DWORDs pointed by the codec data buffer.
+  UINT32 Reserved;           ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+  AZALIA_HEADER Header;      ///< AZALIA PCH header
+  UINT32        *Data;       ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
+/// Refer to the definition of PCH_INT_PIN
+///
+typedef enum {
+  SiPchNoInt,        ///< No Interrupt Pin
+  SiPchIntA,
+  SiPchIntB,
+  SiPchIntC,
+  SiPchIntD
+} SI_PCH_INT_PIN;
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+  UINT8        Device;                  ///< Device number
+  UINT8        Function;                ///< Device function
+  UINT8        IntX;                    ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
+  UINT8        Irq;                     ///< IRQ to be set for device.
+} SI_PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG  64       ///< Number of all PCH devices
+
+
+/** FSP S Configuration
+**/
+typedef struct {
+
+/** Offset 0x0040 - CpuBistData
+  Pointer CPU BIST Data
+**/
+  UINT64                      CpuBistData;
+
+/** Offset 0x0048 - CpuMpPpi
+  <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
+  If not NULL, FSP will use the boot loader's implementation of multiprocessing.
+  See section 5.1.4 of the FSP Integration Guide for more details.
+**/
+  UINT64                      CpuMpPpi;
+
+/** Offset 0x0050 - Reserved
+**/
+  UINT8                       PmcWdtTimerEn;
+
+/** Offset 0x0051 - Reserved
+**/
+  UINT8                       UnusedUpdSpace0[6];
+
+/** Offset 0x0057 - Reserved
+**/
+  UINT8                       ReservedFspsUpd[1];
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+  FSP_UPD_HEADER              FspUpdHeader;
+
+/** Offset 0x0020
+**/
+  FSPS_ARCH2_UPD              FspsArchUpd;
+
+/** Offset 0x0040
+**/
+  FSP_S_CONFIG                FspsConfig;
+
+/** Offset 0x0058
+**/
+  UINT8                       UnusedUpdSpace1[6];
+
+/** Offset 0x005E
+**/
+  UINT16                      UpdTerminator;
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif