Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36087 )
Change subject: soc/intel/tigerlake: Do initial SoC commit ......................................................................
Patch Set 8:
(21 comments)
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/boo... File src/soc/intel/tigerlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/boo... PS8, Line 61: static uint8_t get_dev_revision(pci_devfn_t dev) duplicated, can be merged with other socs
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/chi... PS8, Line 72: switch (dev->path.pci.devfn) { which datasheet(s) was/were consultated to create this array?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/cpu... File src/soc/intel/tigerlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/cpu... PS8, Line 72: msr = rdmsr(IA32_MISC_ENABLE); which datasheet(s) was/were consultated to create this?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/cpu... PS8, Line 130: /* Set PM1 timer IO port and enable*/ missing space
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/cpu... PS8, Line 239: smm_lock(); why is it done here?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/fin... File src/soc/intel/tigerlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/fin... PS8, Line 45: pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); why is it done in finalize?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/fin... PS8, Line 51: if (config->pch_isclk) what is handled here?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/fin... PS8, Line 73: * point and hence removed from the root bus. pcidev_path_on_root thus which datasheet(s) was/were consultated to create this?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/fin... PS8, Line 85: if (config->s0ix_enable) { which datasheet(s) was/were consultated to create this?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/gsp... File src/soc/intel/tigerlake/gspi.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/gsp... PS8, Line 24: return PCH_DEVFN_GSPI0; which datasheet(s) was/were consultated to create this array?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/i2c... File src/soc/intel/tigerlake/i2c.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/i2c... PS8, Line 23: case PCH_DEVFN_I2C0: which datasheet(s) was/were consultated to create this array?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/gpe.h:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/inc... PS8, Line 20: #define GPE0_DW0_00 0 which datasheet(s) was/were consultated to create this?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/gpio_defs.h:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/inc... PS8, Line 47: #define GPP_G0_IRQ 0x18 which datasheet(s) was/were consultated to create this?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/usb.h:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/inc... PS8, Line 22: /* Per Port HS Transmitter Emphasis */ which datasheet(s) was/were consultated to create this?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/loc... File src/soc/intel/tigerlake/lockdown.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/loc... PS8, Line 20: which datasheet(s) was/were consultated to create this? Why is only PMC handled here?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/p2s... File src/soc/intel/tigerlake/p2sb.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/p2s... PS8, Line 29: * Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband which datasheet(s) was/were consultated to create this?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/smi... File src/soc/intel/tigerlake/smihandler.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/smi... PS8, Line 82: pch_disable_heci(); which datasheet(s) was/were consultated? Why it it done in SMM?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/spi... File src/soc/intel/tigerlake/spi.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/spi... PS8, Line 23: case PCH_DEVFN_SPI: which datasheet(s) was/were consultated to create this array?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/sys... File src/soc/intel/tigerlake/systemagent.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/sys... PS8, Line 31: { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, which datasheet(s) was/were consultated to create this array?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/uar... File src/soc/intel/tigerlake/uart.c:
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/uar... PS8, Line 31: PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ which datasheet(s) was/were consultated to create this array?
https://review.coreboot.org/c/coreboot/+/36087/8/src/soc/intel/tigerlake/uar... PS8, Line 61: return pcidev_path_on_root(PCH_DEVFN_UART0); which datasheet(s) was/were consultated to create this array?
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Patrick Rudolph (Code Review)