[M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...
Attention is currently required from: Jason Glenesk, Raul Rangel, EricKY Cheng, Matt DeVillier, Fred Reitberger, Felix Held.
Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 )
Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ......................................................................
Patch Set 21:
(1 comment)
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/ab26a0bf_99728c3c PS16, Line 393: #else
I assume below behavior is your suggestion?
Yes, only tables B through F should be conditionally included by `#if (CONFIG(FEATURE_DYNAMIC_DPTC))`. All boards require normal and low/no battery modes to properly support that feature, so they must be included in every build.
It is a requirement that low/no battery boot is supported on all Skyrim devices/variants, so we can't exclude those tables if `FEATURE_DYNAMIC_DPTC` is enabled. We also do not want the default and low/now battery entries duplicated.
Since those tables are missing values that are required to use the same (expanded) macro, please work with AMD to determine what the missing values are. They may be the same values that are already defined for Table A, but that needs to be verified by AMD.
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Tim Van Patten (Code Review)