Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27678
Change subject: sb/intel/common: Improve TCO code ......................................................................
sb/intel/common: Improve TCO code
* Use register access like on soc/intel * Fix comment spelling * Report unhandled TCO bits in SMM (was dead code)
Change-Id: I5f0b439325227f3fb9f409a56f66256b5a9587d0 Signed-off-by: Patrick Rudolph siro@das-labor.org --- M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c 3 files changed, 14 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/27678/1
diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index ac72eba..06659fa 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -163,18 +163,22 @@ */ u32 reset_tco_status(void) { - u32 reg32; + u16 tco1_sts; + u16 tco2_sts;
- reg32 = read_pmbase32(TCO1_STS); + tco1_sts = read_pmbase16(TCO1_STS); + write_pmbas16(TCO1_STS, tco1_sts); + /* - * set status bits are cleared by writing 1 to them, but don't + * Status bits are cleared by writing 1 to them, but don't * clear BOOT_STS before SECOND_TO_STS. */ - write_pmbase32(TCO1_STS, reg32 & ~BOOT_STS); - if (reg32 & BOOT_STS) - write_pmbase32(TCO1_STS, BOOT_STS); + tco2_sts = read_pmbase16(TCO2_STS); + write_pmbas16(TCO2_STS, tco2_sts & ~BOOT_STS); + if (tco2_sts & BOOT_STS) + write_pmbas16(TCO2_STS, BOOT_STS);
- return reg32; + return (tco2_sts << 16) | tco1_sts; }
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 273e0f8..47fa103 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -96,8 +96,8 @@ #define C3_RES 0x54 #define TCO1_STS 0x64 #define DMISCI_STS (1 << 9) -#define BOOT_STS (1 << 18) #define TCO2_STS 0x66 +#define BOOT_STS (1 << 2) #define TCO1_CNT 0x68 #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index fb2fe59..9dfbaa9 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -417,16 +417,15 @@ * resolute answer would be to power down the * box. */ - printk(BIOS_DEBUG, "Switching back to RO\n"); + printk(BIOS_DEBUG, "Switching BIOS_CNTL back to RO\n"); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); - } else if (!tco_sts) { + } else dump_tco_status(tco_sts); - } }
static void southbridge_smi_periodic(void)