New patch to review for coreboot: 3632277 baytrail: reboot with EC in S0 with no MRC cache and EC in RW

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5040

-gerrit

commit 3632277952153530952c4448e11a11276c72bb5e
Author: Aaron Durbin 
Date:   Thu Jan 9 14:35:41 2014 -0600

baytrail: reboot with EC in S0 with no MRC cache and EC in RW

This improves boot time in 2 ways for a firmware upgrade:

1. Normally MRC would detect the S0 state without an MRC cache
       even though it's told to the S5 path. When it observes this
       state a cold reset occurs. The cold reset stays in S5 for
       at least 4 seconds which is time observed by the end user.

2. As the EC was running RW code before the reset after firmware
       upgrade it will still be running the older RW code. Vboot will
       then reboot the EC and the whole system to put the EC into RO
       mode so it can handle the RW update.

The issues are mitigated by detecting the system is in S0 with
    no MRC cache and the EC isn't in RO mode. Therefore we can do the
    reboot without waiting the 4 secs and the EC is running RO so
    the 2nd reboot is not necessary.

BUG=chrome-os-partner:24133
    BRANCH=rambi,squawks
    TEST=Booted. Updated firmware while in OS. Rebooted. Noted the
         EC reboot before MRC execution.

Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe
    Signed-off-by: Aaron Durbin 
    Reviewed-on: https://chromium-review.googlesource.com/182061
    Reviewed-by: Duncan Laurie 
---
 src/soc/intel/baytrail/romstage/raminit.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 9b0d892..d49735b 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -31,6 +31,8 @@
 #include <baytrail/pci_devs.h>
 #include <baytrail/reset.h>
 #include <baytrail/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>

#if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -138,6 +140,12 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
    	reset_system();
    } else {
    	printk(BIOS_DEBUG, "No MRC cache found.\n");
+#if CONFIG_EC_GOOGLE_CHROMEEC
+		if (prev_sleep_state == 0) {
+			/* Ensure EC is running RO firmware. */
+			google_chromeec_check_ec_image(EC_IMAGE_RO);
+		}
+#endif
    }

mrc_entry = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab,