New patch to review for coreboot: 03c3079 chromeec: Clear post code before reboot to RO

[Marc Jones]

Marc Jones ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9176

-gerrit

commit 03c3079ceb25cb9505c3b1120bf71996fc838e49
Author: Duncan Laurie 
Date:   Fri Aug 29 15:32:55 2014 -0700

chromeec: Clear post code before reboot to RO

When doing an EC requested reboot to RO mode clear the
    saved post code in order to prevent confusing events in
    the log where the system is rebooted intentionally.

BUG=chrome-os-partner:28234
    BRANCH=none
    TEST=build and boot on samus, run FAFT, check for odd
    eventlog entries about last post code 0x31 when it is
    rebooted during samus romstage entry point.

Original-Change-Id: I8bedc611712424bf1044cdca1972e34ffdd51abd
    Original-Signed-off-by: Duncan Laurie 
    Original-Reviewed-on: https://chromium-review.googlesource.com/215681
    Original-Reviewed-by: Aaron Durbin 
    (cherry picked from commit e32d7a7e54e7006b84509dbc2bfe9b4b022eba71)
    Signed-off-by: Marc Jones

Change-Id: Iad816669fb4054260f995f6f0bfb140121aaddff
---
 src/ec/google/chromeec/ec.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 7d35a04..1fadeec 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -146,6 +146,7 @@ void google_chromeec_check_ec_image(int expected_type)
    	cec_cmd.cmd_size_in = sizeof(reboot_ec);
    	cec_cmd.cmd_size_out = 0; /* ignore response, if any */
    	printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n");
+		post_code(0); /* clear current post code */
    	google_chromeec_command(&cec_cmd);
    	udelay(1000);
    	hard_reset();
@@ -451,6 +452,7 @@ void google_chromeec_init(void)
    	cec_cmd.cmd_size_in = sizeof(reboot_ec);
    	cec_cmd.cmd_size_out = 0; /* ignore response, if any */
    	printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n");
+		post_code(0); /* clear current post code */
    	google_chromeec_command(&cec_cmd);
    	udelay(1000);
    	hard_reset();