Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61771 )
Change subject: libpayload: Export PCIe config info from coreboot to libpayload ......................................................................
libpayload: Export PCIe config info from coreboot to libpayload
Export PCIe config base info to payloads through coreboot tables. Fill PCIe config base, ATU address and config size in cbmem entry.
Signed-off-by: Prasad Malisetty quic_pmaliset@quicinc.com Change-Id: I7ad799f2f29bbcdeb113e6ea174151937fd199af --- M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 36 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/61771/1
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index eba4b892..697496a 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -145,6 +145,7 @@
/* Pointer to FMAP cache in CBMEM */ uintptr_t fmap_cache; + uintptr_t pci_config_info;
#if CONFIG(LP_PCI) struct pci_access pacc; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index f8b6f16..9f0a7d4 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -263,6 +263,9 @@ case CBMEM_ID_MEM_CHIP_INFO: info->mem_chip_base = cbmem_entry->address; break; + case CBMEM_ID_PCIE: + info->pci_config_info = cbmem_entry->address; + break; default: break; } diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index d4191e3..173899b 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -80,6 +80,7 @@ #define CBMEM_ID_SMM_COMBUFFER 0x53534d32 #define CBMEM_ID_TYPE_C_INFO 0x54595045 #define CBMEM_ID_MEM_CHIP_INFO 0x5048434D +#define CBMEM_ID_PCIE 0x50434945
#define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -153,6 +154,7 @@ { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}, \ { CBMEM_ID_FSP_LOGO, "FSP LOGO "}, \ { CBMEM_ID_SMM_COMBUFFER, "SMM COMBUFFER"}, \ - { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"},\ - { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"} + { CBMEM_ID_TYPE_C_INFO, "TYPE_C INFO"}, \ + { CBMEM_ID_MEM_CHIP_INFO, "MEM CHIP INFO"}, \ + { CBMEM_ID_PCIE, "PCIE"} #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 91da8e0..8b41dfb 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -328,6 +328,12 @@ struct lb_gpio gpios[0]; };
+struct pci_mmio_config_info { + uint64_t config_base; + uint64_t atu_base; + uint32_t config_size; +}; + struct lb_range { uint32_t tag; uint32_t size; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index e77c60a..32e436d 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -21,6 +21,8 @@ void lb_add_serial(struct lb_serial *serial, void *data); void lb_add_console(uint16_t consoletype, void *data);
+void add_pci_mmio_config_info(struct lb_header *header); + /* Define this in mainboard.c to add board-specific table entries. */ void lb_board(struct lb_header *header);
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d0cba80..2d37261 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -92,6 +92,21 @@ return mem; }
+void add_pci_mmio_config_info(struct lb_header *header) +{ + struct pci_mmio_config_info *pci_info; + + pci_info = cbmem_add(CBMEM_ID_PCIE, sizeof(*pci_info)); + if (pci_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for PCI info missing\n"); + return; + } + + pci_info->config_base = CONFIG_MMIO_BASE_ADDRESS; + pci_info->atu_base = CONFIG_MMIO_PCI_ATU_BASE; + pci_info->config_size = CONFIG_MMIO_LENGTH; +} + void lb_add_serial(struct lb_serial *new_serial, void *data) { struct lb_header *header = (struct lb_header *)data; @@ -486,6 +501,11 @@ if (CONFIG(CHROMEOS)) lb_gpios(head);
+ /* Pass pci config base window */ + if ((CONFIG_MMIO_BASE_ADDRESS != 0) | + (CONFIG_MMIO_LENGTH > 0)) + add_pci_mmio_config_info(head); + /* pass along VBNV offsets in CMOS */ if (CONFIG(VBOOT_VBNV_CMOS)) lb_table_add_vbnv_cmos(head);