Patch set updated for coreboot: 84a99a2 nvidia/ck804: Fix FTBFS with AMD Family 10h systems

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8269

-gerrit

commit 84a99a2af2b9fae562ee4b7aeaaf77878aad2709
Author: Timothy Pearson 
Date:   Fri Jan 23 20:29:46 2015 -0600

nvidia/ck804: Fix FTBFS with AMD Family 10h systems

Change-Id: I85d005edba44c503c49917d4b928e5c9c5900059
    Signed-off-by: Timothy Pearson 
---
 src/southbridge/nvidia/ck804/early_setup_car.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index 9ba98c9..48bfa41 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -1,6 +1,8 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright (C) 2015 Timothy Pearson , Raptor Engineering
+ *
  * Copyright (C) 2004 Tyan Computer
  * Written by Yinghai Lu  for Tyan Computer.
  *
@@ -18,12 +20,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */

+#if IS_ENABLED( CONFIG_NORTHBRIDGE_AMD_AMDK8 )
 static int set_ht_link_ck804(u8 ht_c_num)
 {
    unsigned vendorid = 0x10de;
    unsigned val = 0x01610169;
    return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
 }
+#endif

static void setup_ss_table(unsigned index, unsigned where, unsigned control,
    		   const unsigned int *register_values, int max)
@@ -46,6 +50,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
    val |= 1;
    outl(val, control);
 }
+#endif

#define ANACTRL_IO_BASE 0x3000
 #define ANACTRL_REG_POS 0x68
@@ -297,6 +302,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
    		PCI_DEV(busn[j], CK804B_DEVN_BASE, 0), io_base[j]);
    }

+#if IS_ENABLED( CONFIG_NORTHBRIDGE_AMD_AMDK8 )
    for (j = 0; j < ck804_num; j++) {
    	/* PCI-E (XSPLL) SS table 0x40, x044, 0x48 */
    	/* SATA  (SPPLL) SS table 0xb0, 0xb4, 0xb8 */
@@ -314,6 +320,7 @@ static void ck804_early_setup(unsigned ck804_num, unsigned *busn,
    		       io_base[j] + ANACTRL_IO_BASE + 0xc8,
    		       cpu_ss_tbl, 64);
    }
+#endif
 }

static int ck804_early_setup_x(void)
@@ -340,7 +347,11 @@ static int ck804_early_setup_x(void)
    ck804_early_setup(ck804_num, busn, io_base);
    ck804_early_clear_port(ck804_num, busn, io_base);

+#if IS_ENABLED( CONFIG_NORTHBRIDGE_AMD_AMDK8 )
    return set_ht_link_ck804(4);
+#else
+	return 0
+#endif
 }

void hard_reset(void)