[XS] Change in coreboot[main]: soc/intel/pantherlake: Remove hardcoded value for child nodes

[Sowmya Aralguppe (Code Review)]

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik.

Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/85531?usp=email )

Change subject: soc/intel/pantherlake: Remove hardcoded value for child nodes
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Patch Set 4:

(1 comment)

File src/soc/intel/pantherlake/crashlog.c:

https://review.coreboot.org/c/coreboot/+/85531/comment/65c9b5d0_e1415732?usp... :
PS4, Line 319: 	cpu_cl_disc_tab.header.fields.count = CRASHLOG_NODES_COUNT;
> I'm wondering why the previously discussed items are now being ignored. […]

We hardcoded the child nodes to 2 to match previous x32 implementation. 
Summary : MTL has 5 crash nodes for different dielets in the North only. 
1)      PUNIT
2)      SOCN
3)      DMU
4)      Compute Die
5)      Graphics Die (GCD)
6)      Adamantine Die (ADM) – e RAM (This is not part of the MTL as of now)
But the crash log discovery for Graphics die (5th child node ) had incorrect offset and buffer size for storing crash record. I did not debug this further. This might be because bios is not configuring discovery table for graphics Die properly or it has completely disabled crashlog for Graphics die. Since we wanted the bert file to match the previous implementation x32 (which was iterating only 2 times due to the bug in the pointer implementation which went away when we converted to x64),we read only PUNIT and SOCN crashlog into SRAM  even though DMU and compute Die were having valid crash record.
Coming back : The count should be read from the discovery table always and should not be hardcoded. For PTL the count is just 1 which is at the offset 0x50 and the record buffer is 0x12ec dwords. In the south PCD handled by PMC and does not belong to CPU crashlog handled by PUNIT