[XS] Change in coreboot[main]: soc/intel/meteorlake: Configure DDR5 Physical channel width to 64

[Arthur Heymans (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun.

Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84085?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Code-Review+1 by Paul Menzel, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)

Change subject: soc/intel/meteorlake: Configure DDR5 Physical channel width to 64
......................................................................

soc/intel/meteorlake: Configure DDR5 Physical channel width to 64

A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.

This is the same fix as be5dc3daa "soc/intel/alderlake: Configure DDR5
Physical channel width to 64"

Building with GCC LTO cought this buffer overflow when assigning SPD
addresses to a buffer.

Change-Id: Ief6018e4dcce6b26804ff864cdfe116f0f90d545
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/meteorlake/meminit.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/84085/2