[M] Change in coreboot[master]: soc/intel/meteorlake: Update CSE firmware status registers

[Kapil Porwal (Code Review)]

Attention is currently required from: Tarun Tuli, Jamie Ryu, Subrata Banik, Ravishankar Sarawadi, Sridhar Siricilla.

Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69577 )

Change subject: soc/intel/meteorlake: Update CSE firmware status registers
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Patch Set 1:

(4 comments)

File src/soc/intel/meteorlake/me.c:

https://review.coreboot.org/c/coreboot/+/69577/comment/899fd21b_ecee1320 
PS1, Line 55: uint32_t btg_profile		: 1;
It is a 3-bit field as per the doc.

https://review.coreboot.org/c/coreboot/+/69577/comment/8e4ca89e_010850c8 
PS1, Line 59: uint32_t bsp_bpm_exe_sts        : 4;
1-bit field

https://review.coreboot.org/c/coreboot/+/69577/comment/a465cdd9_8a6ea19e 
PS1, Line 60: uint32_t btg_token_applied	: 4;
1-bit field

https://review.coreboot.org/c/coreboot/+/69577/comment/005d1fc1_b05ae067 
PS1, Line 72: manuf_lock
> It is available as part of HFSTS6 register definition (Table-19). […]

Got it