Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 )

Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices
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Patch Set 20:
> Patch Set 20:
> > Patch Set 20: Code-Review-2
> >
> > (1 comment)
> >
> > southbridge/intel/common has code to do exactly this, besides that you may want to avoid generating the the legacy PIC entries. You just need implement the function to map int pin to int line.
>
> We had this discussion earlier here : https://review.coreboot.org/c/coreboot/+/34089/9//COMMIT_MSG#14
>
> The idea is to create a interrupt table for PCI IOAPIC mapping , which can we passed to FSP to do the IRQ programming + help generate a APCI package with same info to be passed in _PRT. the implementation also takes care of following IRQ assignment rules:
> For single function PCI device capable of generating
> interrupt, use INTA(IRQ16)
> For multi function PCI device capable of generating
> interrupt, at least one should use INTA(IRQ16)
> LPSS controllers need to be assigned unique IRQs i.e
> no LPSS controllers can have same IRQ# mapped to them.

I get that the FSP needs a specific format to set up those PIN/IRQ_routes (and the FSP integration documentation is severely lacking in that regard!!!) and that you need the code below to provide that format. But the ACPI generation does not need to be reinvented. You could just implement a intel_common_map_pirq() based on the code you have here and reuse existing code for ACPI generation, which this patchseries does not do.