Change in coreboot[master]: mb/google/brya/var/vell: update gpio override

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Kevin Chiu, Shon Wang.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59305 )

Change subject: mb/google/brya/var/vell: update gpio override
......................................................................

Patch Set 8:

(3 comments)

File src/mainboard/google/brya/variants/vell/gpio.c:

https://review.coreboot.org/c/coreboot/+/59305/comment/e27f412f_6f438a49 
PS8, Line 10: /* A6  : ESPI_ALERT1# ==> ESPI_ALERT1 */
            : 	PAD_CFG_GPI(GPP_A6, NONE, DEEP),
I don't think we use ESPI Alert1 on chrome EC platforms?

https://review.coreboot.org/c/coreboot/+/59305/comment/bb128d9b_a8a75ac0 
PS8, Line 17: /* B2  : VRALERT# ==> RGB_RST_ODL */
            : 	PAD_CFG_GPI(GPP_B2, NONE, DEEP),
Is this used to reset something or to read the reset state? It is programmed as an input here, so I am guessing it is for reading the reset state?

https://review.coreboot.org/c/coreboot/+/59305/comment/035cceb3_cdd28ecb 
PS8, Line 151: 
You probably want to consider having a romstage GPIO table too, for the SSD PERST# deassertion, e.g.:

```
static const struct pad_config romstage_gpio_table[] = {
        /* B4  : PROC_GP3 ==> SSD_PERST_L */
        PAD_CFG_GPO(GPP_B4, 1, DEEP),
};

const struct pad_config *variant_romstage_gpio_table(size_t *num)
{
        *num = ARRAY_SIZE(romstage_gpio_table);
        return romstage_gpio_table;
}
```

otherwise the FSP may not find anything downstream of the root port and thus disable that root port.