Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 )
Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/#/c/19759/15/src/soc/intel/common/block/gpio/gpi... File src/soc/intel/common/block/gpio/gpio.c:
PS15, Line 68: GPIO_MAX_NUM_PER_GROUP
I'll add this as a field inside the community.
I looked across GPIOs in different SOC EDS. Although different groups have different pin count - for example, GPA has 24 and GPD has 12 , but as long as they are less than 32 which is the register size, they still will be bit mapped into 1 register. In this function and gpio_configure_owner, the pin parameter passed is the pin offset within this community or group. So I think we can still use the macro GPIO_MAX_NUM_PER_GROUP to get the max number which is 24 in example above and not have a new field added to get this number per group or community.
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Hannah Williams (Code Review)