[XS] Change in coreboot[main]: soc/intel/common/block/cpu: Fix number of way computation regression

[Jérémy Compostella (Code Review)]

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Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83948?usp=email )

Change subject: soc/intel/common/block/cpu: Fix number of way computation regression
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Patch Set 6:

(1 comment)

File src/soc/intel/common/block/cpu/car/cache_as_ram.S:

https://review.coreboot.org/c/coreboot/+/83948/comment/75089609_f4b1397b?usp... :
PS5, Line 526: 	xor	%edx, %edx
> How does that matter, since line #528 will copy EAX into EDX anyway?

Line #528 is indeed going to copy %eax to %edx but more importantly line #527 is using %edx per x86 div instruction specification and %edx is not 0 because you set it to 1 line #517.

As explained in the commit message, the `div` instruction specification is clear, it divides the 64-bit long %edx:%eax register combination by its parameter (here %ecx). As result of commit  16ab9bdcd578612bb3822373547f939eb90afd82, %edx contains 0x1 when the code reaches line 526.

Below is the code annotated with the value I dumped through some instrumentation. I used `$CONFIG_DCACHE_RAM_SIZE = 0x200000` and a LLC with a way size of 0x180000.

mov	$CONFIG_DCACHE_RAM_SIZE, %eax ; 0x200000 -> eax
    div	%ecx			      ; 0x100200000 / 0x180000 = 0xaac
    mov	%eax, %edx 		      ; edx = 0xaac
    mov	%eax, %ecx		      ; ecx = 0xaac
    movl	$0x01, %eax		      ; eax = 1
    shl	%cl, %eax		      ; eax = 0x1000
    subl	$0x01, %eax		      ; 0xfff

https://www.felixcloutier.com/x86/div