[L] Change in coreboot[main]: soc/intel/ptl: Add GPE1 defines

[Subrata Banik (Code Review)]

Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Saurabh Mishra.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )

Change subject: soc/intel/ptl: Add GPE1 defines
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Patch Set 4:

(2 comments)

File src/soc/intel/pantherlake/include/soc/gpe.h:

https://review.coreboot.org/c/coreboot/+/84297/comment/0887b89f_90237e3d?usp... :
PS4, Line 30: 146
unable to follow why the index is 145 or 0x91 ?

ideally this should be a bit mask as applicable to GPE1_xxx register

File src/soc/intel/pantherlake/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/84297/comment/ab4e9862_62eb0bec?usp... :
PS4, Line 285: #if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)
             : 	uint32_t gpe1_sts[3];
             : 	uint32_t gpe1_en[3];
             : #endif
please maintain the order. GPE1 should be ahead in this structure