[M] Change in coreboot[master]: [WIP] include/post_code: Reorganize POST code to range specific header

[Yuchen He (Code Review)]

Yuchen He has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76099?usp=email )

Change subject: [WIP] include/post_code: Reorganize POST code to range specific header
......................................................................

[WIP] include/post_code: Reorganize POST code to range specific header

Relocate POST code macros to a main post_code folder with multiple
header files. In each is a description of the header and POST code
ranges proposed by Martin Roth.

This is an initial implementaion and highly work in progress. Hence,
critiques, opinions and ideas are welcome!

Change-Id: Ic140f6bd46f6de2ba31db453aac5cbfd3bd4be84
Signed-off-by: lilacious 
---
A src/include/post_code/acpi.h
A src/include/post_code/bootstage.h
A src/include/post_code/coreboot.h
A src/include/post_code/debug.h
A src/include/post_code/driver.h
A src/include/post_code/error.h
A src/include/post_code/mainboard.h
A src/include/post_code/post_code_unregulated.h
A src/include/post_code/soc.h
A src/include/post_code/vendorcode.h
10 files changed, 148 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/76099/1

diff --git a/src/include/post_code/acpi.h b/src/include/post_code/acpi.h
new file mode 100644
index 0000000..0f46d95
--- /dev/null
+++ b/src/include/post_code/acpi.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file contains ACPI related POST codes.
+ *
+ * ACPI POST code range is:
+ *	0x80 to 0x87
+ */
+#ifndef _ACPI_H_
+#define _ACPI_H_
+
+#endif
diff --git a/src/include/post_code/bootstage.h b/src/include/post_code/bootstage.h
new file mode 100644
index 0000000..7b2801f
--- /dev/null
+++ b/src/include/post_code/bootstage.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file contains POST codes related to various coreboot stages.
+ *
+ * POST codes ranges of these stages are:
+ *	0x10 to 0x1f	- bootblock
+ *	0x20 to 0x2f	- romstage
+ *	0x30 to 0x33	- postcar
+ *	0x34 to 0x3f	- ramstage
+ *	0x40 to 0x4f	- ramstage hardwaremain boot stages
+ *	0xf0 to 0xf7	- SMM
+ */
+#ifndef _BOOTSTAGE_H_
+#define _BOOTSTAGE_H_
+
+#endif
diff --git a/src/include/post_code/coreboot.h b/src/include/post_code/coreboot.h
new file mode 100644
index 0000000..4792c51
--- /dev/null
+++ b/src/include/post_code/coreboot.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file contains coreboot POST codes excluding Stages.
+ *
+ * Coreboot POST code ranges are:
+ *	0x01 to 0x07	- coreboot startup code & common
+ *	0x08 to 0x0b	- coreboot console
+ *	0xcb		- coreboot identifier
+ *	0xf8 to 0xfe	- end of coreboot code
+ *	0xff		- coreboot finished, jump to payload
+ */
+
+#ifndef _COREBOOT_H_
+#define _COREBOOT_H_
+
+#endif
diff --git a/src/include/post_code/debug.h b/src/include/post_code/debug.h
new file mode 100644
index 0000000..b9e3296
--- /dev/null
+++ b/src/include/post_code/debug.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file contains POST codes related to debugging.
+ * These are never enabled by default.
+ *
+ * Debug POST code range is:
+ *	0xd0 to 0xdf
+ */
+
+#ifndef _DEBUG_H_
+#define _DEBUG_H_
+
+#endif
diff --git a/src/include/post_code/driver.h b/src/include/post_code/driver.h
new file mode 100644
index 0000000..61f2f66
--- /dev/null
+++ b/src/include/post_code/driver.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file contains Driver/SuperIO specific POST codes and ID.
+ *
+ * Driver/SuperIO ID is:
+ *	0x70		- is followed by an ID byte
+ *
+ * Driver/SuperIO POST code is:
+ *	0x71 to 7f
+ */
+
+#ifndef _DRIVER_H_
+#define _DRIVER_H_
+
+
+#endif
diff --git a/src/include/post_code/error.h b/src/include/post_code/error.h
new file mode 100644
index 0000000..f6dc857
--- /dev/null
+++ b/src/include/post_code/error.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file contains error related POST codes.
+ *
+ * Error POST code range is:
+ *	0xe0 to 0xef
+ */
+#ifndef _SMM_H_
+#define _SMM_H_
+
+#endif
diff --git a/src/include/post_code/mainboard.h b/src/include/post_code/mainboard.h
new file mode 100644
index 0000000..930124f
--- /dev/null
+++ b/src/include/post_code/mainboard.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file contains mainboard specific POST codes.
+ *
+ * Mainboard POST code range is:
+ *	0x50 to 0x5f
+ */
+
+#ifndef _MAINBOARD_H_
+#define _MAINBOARD_H_
+
+#endif
diff --git a/src/include/post_code/post_code_unregulated.h b/src/include/post_code/post_code_unregulated.h
new file mode 100644
index 0000000..94ad38b
--- /dev/null
+++ b/src/include/post_code/post_code_unregulated.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file contains unregulated POST codes.
+ *
+ * Unregulated POST code ranges are:
+ *	0x00		- Clears up port 0x80
+ *	0x88 to 0x8f	- May be used anywhere for any purpose
+ */
+
+#ifndef _POST_CODE_UNREGULATED_H_
+#define _POST_CODE_UNREGULATED_H_
+
+/**
+ * \brief Not an actual post-code - used to clear port80h
+ *
+ */
+#define POSTCODE_CODE_CLEAR				0x00
+
+#endif
diff --git a/src/include/post_code/soc.h b/src/include/post_code/soc.h
new file mode 100644
index 0000000..e863647
--- /dev/null
+++ b/src/include/post_code/soc.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file contains SoC specific POST codes.
+ *
+ * SoC POST code range is.
+ *	0x60 to 0x6f
+ */
+#ifndef _SOC_H_
+#define _SOC_H_
+
+#endif
diff --git a/src/include/post_code/vendorcode.h b/src/include/post_code/vendorcode.h
new file mode 100644
index 0000000..f7122e0
--- /dev/null
+++ b/src/include/post_code/vendorcode.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file contains vendorcode call relating POST codes such as
+ * FSP, AGESA, etc.
+ *
+ * Vendorcode POST code range is:
+ *	0x90 to 0x9f
+ */
+
+#ifndef _VENDORCODE_H_
+#define _VENDORCODE_H_
+
+#endif