Change in coreboot[master]: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55225 )
Change subject: soc/intel/alderlake/romstage: Refactor soc_memory_init_params function ......................................................................
soc/intel/alderlake/romstage: Refactor soc_memory_init_params function
This patch create separate helper functions to fill-in required FSP-M UPDs as per IP initialization categories.
This would help to increase the code readability and in future meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly.
TEST=FSP-M UPD dump shows no change without and with this code change.
Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 174 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/55225/1
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index ba6e036..8d39c74 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -60,13 +60,11 @@ } }
-static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, +static void fill_igd_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { - const struct device *dev; - unsigned int i; + const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
- dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev)) m_cfg->InternalGfx = 1; else @@ -75,30 +73,6 @@ /* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */ m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? IGD_SM_60MB : 0;
- m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->SaGv = config->SaGv; - m_cfg->RMT = config->RMT; - - /* CpuRatio Settings */ - if (config->cpu_ratio_override) - m_cfg->CpuRatio = config->cpu_ratio_override; - else - /* Set CpuRatio to match existing MSR value */ - m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; - - m_cfg->PrmrrSize = get_valid_prmrr_size(); - m_cfg->EnableC6Dram = config->enable_c6dram; - /* Disable BIOS Guard */ - m_cfg->BiosGuard = 0; - - /* UART Debug Log */ - m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; - if (CONFIG(DRIVERS_UART_8250IO)) - m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; - m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; - m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; - /* DP port config */ m_cfg->DdiPortAConfig = config->DdiPortAConfig; m_cfg->DdiPortBConfig = config->DdiPortBConfig; @@ -116,27 +90,88 @@ m_cfg->DdiPort2Ddc = config->DdiPort2Ddc; m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; +}
- /* Image clock: disable all clocks for bypassing FSP pin mux */ - memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); - - /* Enable Hyper Threading */ - m_cfg->HyperThreading = 1; - /* Disable Lock PCU Thermal Management registers */ - m_cfg->LockPTMregs = 0; +static void fill_memory_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + m_cfg->SaGv = config->SaGv; + m_cfg->RMT = config->RMT; /* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */ m_cfg->ChHashMask = 0x30CC; +} + +static void fill_cpu_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + /* CpuRatio Settings */ + if (config->cpu_ratio_override) + m_cfg->CpuRatio = config->cpu_ratio_override; + else + /* Set CpuRatio to match existing MSR value */ + m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; + + m_cfg->PrmrrSize = get_valid_prmrr_size(); + m_cfg->EnableC6Dram = config->enable_c6dram; + /* Enable Hyper Threading */ + m_cfg->HyperThreading = 1; +} + +static void fill_security_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + m_cfg->TmeEnable = CONFIG(INTEL_TME); +} + +static void fill_uart_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + /* UART Debug Log */ + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; + if (CONFIG(DRIVERS_UART_8250IO)) + m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; + m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +} + +static void fill_ipu_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + /* Image clock: disable all clocks for bypassing FSP pin mux */ + memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); +} + +static void fill_smbus_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); /* Enable SMBus controller */ - dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); m_cfg->SmbusEnable = is_dev_enabled(dev); - /* Set debug probe type */ - m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT; +}
+static void fill_misc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* Disable Lock PCU Thermal Management registers */ + m_cfg->LockPTMregs = 0; + + /* Skip CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; + + /* Skip GPIO configuration from FSP */ + m_cfg->GpioOverride = 0x1; +} + +static void fill_audio_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_HDA); m_cfg->PchHdaEnable = is_dev_enabled(dev); - m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; + m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; + m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable; /* * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to * configure GPIO pads for audio. Mainboard is expected to perform all GPIO @@ -147,11 +182,13 @@ memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); - m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode; - m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; - m_cfg->PchHdaIDispCodecDisconnect = !config->PchHdaIDispCodecEnable; +}
- /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ +static void disable_pcie_clksrc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + unsigned int i; + for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; @@ -161,20 +198,47 @@ m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; } +}
- /* PCIE ports */ +static void fill_pch_pcie_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp, CONFIG_MAX_PCH_ROOT_PORTS); +}
- /* CPU PCIE ports */ +static void fill_cpu_pcie_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp, CONFIG_MAX_CPU_ROOT_PORTS); +}
- /* ISH */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); +static void fill_pcie_rp_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ + disable_pcie_clksrc_memory_init_params(m_cfg, config); + + /* Configure PCH PCIE ports */ + fill_pch_pcie_memory_init_params(m_cfg, config); + + /* Configure CPU PCIE ports */ + fill_cpu_pcie_memory_init_params(m_cfg, config); +} + +static void fill_ish_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH); + /* Enable ISH controller */ m_cfg->PchIshEnable = is_dev_enabled(dev); +} + +static void fill_tcss_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + const struct device *dev;
/* Tcss USB */ dev = pcidev_path_on_root(SA_DEVFN_TCSS_XHCI); @@ -189,8 +253,12 @@
dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1); m_cfg->TcssDma1En = is_dev_enabled(dev); +}
- /* USB4/TBT */ +static void fill_usb4_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + const struct device *dev; + dev = pcidev_path_on_root(SA_DEVFN_TBT0); m_cfg->TcssItbtPcie0En = is_dev_enabled(dev);
@@ -202,8 +270,10 @@
dev = pcidev_path_on_root(SA_DEVFN_TBT3); m_cfg->TcssItbtPcie3En = is_dev_enabled(dev); +}
- /* VT-d config */ +static void fill_vtd_memory_init_params(FSP_M_CONFIG *m_cfg) +{ m_cfg->VtdBaseAddress[VTD_GFX] = GFXVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_IPU] = IPUVT_BASE_ADDRESS; m_cfg->VtdBaseAddress[VTD_VTVCO] = VTVC0_BASE_ADDRESS; @@ -230,13 +300,12 @@
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - /* Skip CPU replacement check */ - m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; +}
- m_cfg->TmeEnable = CONFIG(INTEL_TME); - - /* Skip GPIO configuration from FSP */ - m_cfg->GpioOverride = 0x1; +static void fill_trace_memory_init_params(FSP_M_CONFIG *m_cfg) +{ + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
/* CrashLog config */ if (CONFIG(SOC_INTEL_CRASHLOG)) { @@ -245,6 +314,55 @@ } }
+static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* Fill IGD related FSP-M UPDs */ + fill_igd_memory_init_params(m_cfg, config); + + /* Fill Memory related FSP-M UPDs */ + fill_memory_memory_init_params(m_cfg, config); + + /* Fill CPU related FSP-M UPDs */ + fill_cpu_memory_init_params(m_cfg, config); + + /* Fill security related FSP-M UPDs */ + fill_security_memory_init_params(m_cfg); + + /* Fill UART debug related FSP-M UPDs */ + fill_uart_memory_init_params(m_cfg); + + /* Fill IPU related FSP-M UPDs */ + fill_ipu_memory_init_params(m_cfg); + + /* Fill SMBUS related FSP-M UPDs */ + fill_smbus_memory_init_params(m_cfg); + + /* Fill Miscellaneous FSP-M UPDs */ + fill_misc_memory_init_params(m_cfg, config); + + /* Fill Audio related FSP-M UPDs */ + fill_audio_memory_init_params(m_cfg, config); + + /* Fill PCIE related RP FSP-M UPDs */ + fill_pcie_rp_memory_init_params(m_cfg, config); + + /* Fill ISH related FSP-M UPD */ + fill_ish_memory_init_params(m_cfg); + + /* Fill TCSS related FSP-M UPD */ + fill_tcss_memory_init_params(m_cfg); + + /* Fill USB4/TBT related FSP-M UPD */ + fill_usb4_memory_init_params(m_cfg); + + /* Fill VT-d related FSP-M UPD */ + fill_vtd_memory_init_params(m_cfg); + + /* Fill trace related FSP-M UPD */ + fill_trace_memory_init_params(m_cfg); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_alderlake_config *config;
-
Subrata Banik (Code Review)