Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80166?usp=email )
(
8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Include ADL-N ID 5 ......................................................................
soc/intel/alderlake: Include ADL-N ID 5
This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes sean@starlabs.systems Change-Id: I7b9fc64ccf8e2401dcd55607e8f09b348efb3182 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80166 Reviewed-by: Kapil Porwal kapilporwal@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/alderlake/vr_config.c 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 911e1dd..6718e89 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -249,6 +249,7 @@ { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -309,6 +310,7 @@ { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(10, 10) }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 12) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },