New patch to review for coreboot: e8058d9 baytrail: reinitialize spi controller in SMM finalization

[Marc Jones]

Marc Jones ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9296

-gerrit

commit e8058d975cbe181035f3481a1d6d7f0baff9f8d4
Author: Aaron Durbin 
Date:   Sun Feb 9 16:04:06 2014 -0600

baytrail: reinitialize spi controller in SMM finalization

On the SMM APM_CNT_FINALIZE step re-initialize the SPI
    controller so that it can still log events after the SPI
    controller has been locked down.

BUG=chrome-os-partner:24624
    BRANCH=baytrail
    TEST=Built and booted. Events still logged after SPI controller
         has been locked down.

Original-Change-Id: I41a3e12c0398303e74f95eb6df82d5bc4303898b
    Original-Signed-off-by: Aaron Durbin 
    Original-Reviewed-on: https://chromium-review.googlesource.com/185630
    Original-Reviewed-by: Duncan Laurie 
    (cherry picked from commit 28ffb1a9e761cdfeb173bd533684db1011260e0a)
    Signed-off-by: Marc Jones

Change-Id: Ia82753cba9ae4f049de2e81061739efc21d49a1e
---
 src/soc/intel/baytrail/smihandler.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index a2718e2..0641907 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -26,6 +26,7 @@
 #include <device/pci_def.h>
 #include <elog.h>
 #include <halt.h>
+#include <spi-generic.h>

#include <baytrail/pci_devs.h>
 #include <baytrail/pmc.h>
@@ -232,6 +233,23 @@ static void southbridge_smi_gsmi(void)
    *ret = gsmi_exec(sub_command, param);
 }
 #endif
+
+static void finalize(void)
+{
+	static int finalize_done;
+
+	if (finalize_done) {
+		printk(BIOS_DEBUG, "SMM already finalized.\n");
+		return;
+	}
+	finalize_done = 1;
+
+#if CONFIG_SPI_FLASH_SMM
+	/* Re-init SPI driver to handle locked BAR */
+	spi_init();
+#endif
+}
+
 static void southbridge_smi_apmc(void)
 {
    uint8_t reg8;
@@ -282,6 +300,9 @@ static void southbridge_smi_apmc(void)
    	southbridge_smi_gsmi();
    	break;
 #endif
+	case APM_CNT_FINALIZE:
+		finalize();
+		break;
    }

mainboard_smi_apmc(reg8);