[L] Change in coreboot[main]: arch/x86/mmu: Port armv8 MMU to x86_64

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Benjamin Doron, Felix Held, Julius Werner, Subrata Banik.

Patrick Rudolph has posted comments on this change by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/79161?usp=email )

Change subject: arch/x86/mmu: Port armv8 MMU to x86_64
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Patch Set 11:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/79161/comment/bfdb3087_17973486?usp... :
PS11, Line 16: DRAM and MMIO even beyond 4GiB.
> > Can we maybe expand the pt1G. […]

On SPR I need to access a BAR in high MMIO at `0x200ffff90000`. That would increase pt1G.S by factor 64 at least.
By mapping the whole address space ramstage size increases to 2501728 bytes. Not sure if it would fit into the stage cache, but since ACPI S3 isn't supported this is probably not a problem.

Having page tables in CBMEM would keep ramstage size and it should still fit into the stage cache or (as suggested) using BSS and generate the page tables at runtime.