Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84230?usp=email )
Change subject: make same cpu pyhsical address ......................................................................
make same cpu pyhsical address
2 funtions are used to get cpu physical address like below. cpu_phys_address_size soc_phys_address_size And If CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH is defined, it can return different address size like below example) CB log : CPU physical address size: 46 bits OS log : DMAR: Host address width 42 So, need to make one API to use same physical address.
BUG: none TEST: Check same address size in Coreboot log and OS log
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I06c485511fa7f72a445c8aed56d8a470b4772092 --- M src/acpi/acpi_dmar.c M src/arch/x86/cpu_common.c M src/device/pci_device.c M src/include/cpu/cpu.h M src/soc/intel/common/block/systemagent/systemagent.c 5 files changed, 6 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84230/1
diff --git a/src/acpi/acpi_dmar.c b/src/acpi/acpi_dmar.c index 67bca55..9725f2f 100644 --- a/src/acpi/acpi_dmar.c +++ b/src/acpi/acpi_dmar.c @@ -28,7 +28,7 @@ header->length = sizeof(acpi_dmar_t); header->revision = get_acpi_table_revision(DMAR);
- dmar->host_address_width = soc_phys_address_size() - 1; + dmar->host_address_width = cpu_phys_address_size() - 1; dmar->flags = flags;
current = acpi_fill_dmar(current); diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 5f7cd5d..ddedea4 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -47,6 +47,9 @@
unsigned int cpu_phys_address_size(void) { + if (CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH) + return CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH; + if (!(cpu_have_cpuid())) return 32;
@@ -61,14 +64,6 @@ return 32; }
-unsigned int soc_phys_address_size(void) -{ - if (CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH) - return CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH; - - return cpu_phys_address_size(); -} - /* * Get processor id using cpuid eax=1 * return value in EAX register diff --git a/src/device/pci_device.c b/src/device/pci_device.c index a2ad2b3..859f085 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -578,7 +578,7 @@ /* Initialize 64-bit memory resource constraints above 4G. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(2, 0)); res->base = 4ULL * GiB; - res->limit = (1ULL << soc_phys_address_size()) - 1; + res->limit = (1ULL << cpu_phys_address_size()) - 1; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 5f32720..9783976 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -10,7 +10,6 @@ uintptr_t cpu_get_lapic_addr(void); struct bus; unsigned int cpu_phys_address_size(void); -unsigned int soc_phys_address_size(void);
#if ENV_RAMSTAGE #define __cpu_driver __attribute__((used, __section__(".rodata.cpu_driver"))) diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e8d7432..a45f00d 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -323,7 +323,7 @@ uint64_t touud; sa_read_map_entry(pcidev_path_on_root(SA_DEVFN_ROOT), &sa_memory_map[SA_TOUUD_REG], &touud); - const uint64_t len = POWER_OF_2(soc_phys_address_size()) - touud; + const uint64_t len = POWER_OF_2(cpu_phys_address_size()) - touud;
const char *scope = acpi_device_path(dev); acpigen_write_scope(scope);