[M] Change in coreboot[master]: mb/google/brya/var/brya0: update dptf thermal settings

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72867 )

Change subject: mb/google/brya/var/brya0: update dptf thermal settings
......................................................................

mb/google/brya/var/brya0: update dptf thermal settings

Update dptf thermal settings as per suggested by thermal team.
Control fan based on TSR sensors, not based on CPU sensor temperature
which changes too fast.

BRANCH=firmware-brya-14505.B
BUG=b:235311241, b:261749371
TEST=Built and tested on Brya system

Change-Id: I58bc7132086b0776ee191a242bd1302554f3854f
Signed-off-by: Sumeet Pawnikar 
---
M src/mainboard/google/brya/variants/brya0/overridetree.cb
1 file changed, 57 insertions(+), 14 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/72867/1

diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index 5f5e897..4d2624a 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -124,23 +124,48 @@
    			## Active Policy
    			register "policies.active" = "{
    				[0] = {
-						.target = DPTF_CPU,
+						.target = DPTF_TEMP_SENSOR_0,
    					.thresholds = {
-								TEMP_PCT(85, 90),
-								TEMP_PCT(80, 80),
-								TEMP_PCT(75, 70),
-								TEMP_PCT(70, 50),
-								TEMP_PCT(65, 30),
+								TEMP_PCT(75, 97),
+								TEMP_PCT(70, 93),
+								TEMP_PCT(60, 86),
+								TEMP_PCT(52, 80),
+								TEMP_PCT(47, 64),
+								TEMP_PCT(43, 52),
+								TEMP_PCT(40, 40),
    					}
    				},
    				[1] = {
    					.target = DPTF_TEMP_SENSOR_1,
    					.thresholds = {
-								TEMP_PCT(50, 90),
-								TEMP_PCT(48, 70),
-								TEMP_PCT(46, 60),
-								TEMP_PCT(43, 40),
-								TEMP_PCT(40, 30),
+								TEMP_PCT(75, 97),
+								TEMP_PCT(70, 93),
+								TEMP_PCT(60, 86),
+								TEMP_PCT(52, 80),
+								TEMP_PCT(47, 64),
+								TEMP_PCT(43, 52),
+								TEMP_PCT(40, 40),
+						}
+					},
+					[2] = {
+						.target = DPTF_TEMP_SENSOR_2,
+						.thresholds = {
+								TEMP_PCT(82, 97),
+								TEMP_PCT(78, 93),
+								TEMP_PCT(72, 86),
+								TEMP_PCT(60, 80),
+						}
+					},
+					[3] = {
+						.target = DPTF_TEMP_SENSOR_3,
+						.thresholds = {
+								TEMP_PCT(75, 97),
+								TEMP_PCT(70, 93),
+								TEMP_PCT(60, 86),
+								TEMP_PCT(52, 80),
+								TEMP_PCT(47, 64),
+								TEMP_PCT(43, 52),
+								TEMP_PCT(40, 40),
    					}
    				}
    			}"
@@ -148,10 +173,10 @@
    			## Passive Policy
    			register "policies.passive" = "{
    				[0] = DPTF_PASSIVE(CPU,         CPU,           95, 5000),
-					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 75, 5000),
-					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 75, 5000),
+					[1] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_0, 80, 5000),
+					[2] = DPTF_PASSIVE(CPU,		TEMP_SENSOR_1, 80, 5000),
    				[3] = DPTF_PASSIVE(CHARGER,	TEMP_SENSOR_2, 75, 5000),
-					[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 75, 5000),
+					[4] = DPTF_PASSIVE(CPU,         TEMP_SENSOR_3, 80, 5000),
    			}"

## Critical Policy