[XS] Change in coreboot[main]: mb/google/trulo/var/orisa: Configure SEN_MODE_EC_PCH_INT_ODL as input

[Eric Lai (Code Review)]

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83142?usp=email )

Change subject: mb/google/trulo/var/orisa: Configure SEN_MODE_EC_PCH_INT_ODL as input
......................................................................

mb/google/trulo/var/orisa: Configure SEN_MODE_EC_PCH_INT_ODL as input

Configure GPP_R2 as input, no pull according to schematic_20240614.

BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Ic678b77e5489f56d8ff92b265a6ca5852c0f7e8d
Signed-off-by: Amanda Huang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83142
Tested-by: build bot (Jenkins) 
Reviewed-by: Eric Lai 
Reviewed-by: Kapil Porwal 
---
M src/mainboard/google/brya/variants/orisa/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Eric Lai: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/orisa/gpio.c b/src/mainboard/google/brya/variants/orisa/gpio.c
index f8d021a..49fc025 100644
--- a/src/mainboard/google/brya/variants/orisa/gpio.c
+++ b/src/mainboard/google/brya/variants/orisa/gpio.c
@@ -122,7 +122,7 @@
    /* D1  : ISH_GP1 ==> SOC_GSEN2_INT# */
    PAD_CFG_NF_LOCK(GPP_D1, NONE, NF1, LOCK_CONFIG),
    /* D2  : ISH_GP2 ==> SEN_MODE_EC_PCH_INT_ODL */
-	PAD_CFG_NF_LOCK(GPP_D2, NONE, NF1, LOCK_CONFIG),
+	PAD_CFG_GPI_LOCK(GPP_D2, NONE, LOCK_CONFIG),
    /* D3  : NC */
    PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
    /* D4  : NC */